Adder Discussion D6.2 Example 17. s i = c i ^ (a i ^ b i ) c i+1 = a i * b i + c i * (a i ^ b i ) Full Adder (Appendix I)

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Presentation transcript:

Adder Discussion D6.2 Example 17

s i = c i ^ (a i ^ b i ) c i+1 = a i * b i + c i * (a i ^ b i ) Full Adder (Appendix I)

-- Example 17a: 4-bit adder library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; entity adder4a is port( a : in STD_LOGIC_VECTOR(3 downto 0); b : in STD_LOGIC_VECTOR(3 downto 0); cf : out STD_LOGIC; ovf : out STD_LOGIC; s : out STD_LOGIC_VECTOR(3 downto 0) ); end adder4a;

architecture adder4a of adder4a is -- intermediate carries signal c: STD_LOGIC_VECTOR(4 downto 0); begin c(0) <= '0'; s <= a xor b xor c(3 downto 0); c(4 downto 1) <= (a and b) or (c(3 downto 0) and (a xor b)); cf <= c(4); ovf <= c(3) xor c(4); end adder4a;

Aldec Active-HDL Simulation

Full Adder Truth table CiCi AiAi BiBi SiSi C i+1 Behavior C i+1 :S i = C i + A i + B i

Full Adder Block Diagram

4-Bit Adder c :a :b c4:s

-- Example 17a: 4-bit adder library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; entity adder4b is port( a : in STD_LOGIC_VECTOR(3 downto 0); b : in STD_LOGIC_VECTOR(3 downto 0); cf : out STD_LOGIC; ovf : out STD_LOGIC; s : out STD_LOGIC_VECTOR(3 downto 0) ); end adder4b;

architecture adder4b of adder4b is begin process(a,b) variable temp: STD_LOGIC_VECTOR(4 downto 0); variable sv: STD_LOGIC_VECTOR(3 downto 0); variable cfv: STD_LOGIC; begin temp := ('0' & a) +('0' & b); sv := temp(3 downto 0); cfv := temp(4); ovf <= sv(3) xor a(3) xor b(3) xor cfv; cf <= cfv; s <= sv; end process; end adder4b; c :a :b c4:s

Aldec Active-HDL Simulation

-- Example 17c: 4-bit adder library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; entity adder is generic(N:positive := 8); port( a : in STD_LOGIC_VECTOR(N-1 downto 0); b : in STD_LOGIC_VECTOR(N-1 downto 0); s : out STD_LOGIC_VECTOR(N-1 downto 0) ); end adder; architecture adder of adder is begin process(a,b) begin s <= a + b; end process; end adder; N-Bit Adder

Aldec Active-HDL Simulation