Design and Implementation of VLSI Systems (EN1600) Lecture08 Prof. Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison Wesley – Rabaey/Pearson] TexPoint fonts used in EMF. Read the TexPoint manual before you delete this box.: AAA A A

Summary of Shockley model for nMOS for pMOS

Ideal vs. non-ideal idealNon-ideal  Saturation current does not increase quadratically with Vgs  Saturation current lightly increases with increase in Vds

Ideal vs. non-ideal  There is leakage current when the transistor is in cut off  Ids depends on the temperature

Velocity saturation  (V/µm)  c = 1.5  n ( m / s )  sat = 10 5 Constant mobility (slope = µ) Constant velocity At high electric field, drift velocity rolls of due to carrier scattering Empirically:

Alpha model Pc, Pv and alpha are found by fitting the model to the empirical modeling results

Channel length modulation The reverse-bias p-n junction between drain and body forms a depletion region with a width L d that increases with V db Increasing V ds  increases depletion width  decreases effective channel length  increases current Channel length modulation factor (empirical factor)

Leakage current: subthreshold n+ p-type body W L t ox polysilicon gate Subthreshold conduction Tunnel current Junction leakage  Subthreshold leakage is the biggest source in modern transistors 180nm process n =

Leakage current: junction leakage and tunneling Junction leakage: reverse-biased p-n junctions have some leakage. I s depends on doping levels and area and perimeter of diffusion regions Tunneling leakage:  Carriers may tunnel thorough very thin gate oxides  Negligible for older processes (and future processes with high-k dielectrics!)

Impact of temperature Increases in temperature increases leakage current Increases in temperature decreases leakage current

Body effect  V t is sensitive to Vsb -> body effect What is the impact on Vt if we increase/decrease the body bias?

Process variations Both MOSFETs have 30nm channel with 130 dopant atoms in the channel depletion region threshold voltage 0.97Vthreshold voltage 0.57V Process variations impact gate length, threshold voltage, and oxide thickness

Summary  Ideal transistor characteristics  Non-ideal transistor characteristics  Inverter DC transfer characteristics  Simulation with SPICE and integration with L-Edit