1/1/ / faculty of Electrical Engineering eindhoven university of technology Algorithmic Level design in IDaSS dr.ir. Ad C. Verschueren Eindhoven University of Technology section of Information and Communication Systems

1/1/ / faculty of Electrical Engineering eindhoven university of technology Contents Basic idea, (dis)advantages, when to use Algorithms = variables + routines The actual Algorithmic Level language – assignments and commands – test blocks and loops – subroutine calls and returns – clock synchronisation AL block building and debugging environment AL_block

1/1/ / faculty of Electrical Engineering eindhoven university of technology The basic idea Single block describes datapath AND control – local storage with register and RAM-like variables – functionality with structured programming language ‘main’ routine starts after reset (optional) subroutines without parameters (simpler hardware!) Can be placed in RTL environment – tests, controls and writes RTL components – synchronise to clock at specific program points can wait for ‘events’ in environment at these points

1/1/ / faculty of Electrical Engineering eindhoven university of technology Advantages and disadvantages On the positive side: – one AL block can contain a lot of functionality …easy to describe and modify – an AL block simulates faster than RTL equivalent On the negative side: – automatic conversion to HDL not possible (yet) – easy to describe hard-to-synthesize functionality

1/1/ / faculty of Electrical Engineering eindhoven university of technology When to use AL blocks If you don’t want to design RTL (yet) – sub-modules to be designed later – to create dynamic test environments If the functionality is very complex – use AL to find out needed storage and algorithms – specially for control-driven designs If you want to have faster simulation – can be used to hide the actual architecture

1/1/ / faculty of Electrical Engineering eindhoven university of technology Types of routines The ‘main’ routine starts after (system) reset – this routine is optional, startup ‘idle’ if not defined ‘Global’ subroutines externally callable – uses ‘call: name’ command: ‘interrupt’ behaviour – call and return take a clock cycle (to synchronise) ‘Local’ subroutines for internal use only – call and return immediately

1/1/ / faculty of Electrical Engineering eindhoven university of technology Types of variables Local variables – registers: bits, with semaphore, local inc/dec – memories: as RAM, but no ports – assignments take place immediately – name in text starts with underscore like ‘_ACCU’ ANY value in RTL environment – same sources as state controller test expressions async. connector tests only in ‘wait expressions’ – clocked assignments to registers and RAM’s

1/1/ / faculty of Electrical Engineering eindhoven university of technology Algorithmic Level language overview Assignments and commands Conditional execution with test blocks Four types of loops – endless, while..do.., do..until.., counted Subroutine calls and returns Wait statements and wait expressions

1/1/ / faculty of Electrical Engineering eindhoven university of technology AL language: := assignments Targets local/external registers or RAM’s – writing external RAM’s will not be synthesizable – external assignments executed at next clock Wide range of sources within expressions – local registers or RAM locations – clocked values testable by state controllers – external memory locations (not synthesizable) Memory locations addressed with – address expressions in is NOT operator

1/1/ / faculty of Electrical Engineering eindhoven university of technology Assignments question What is the behaviour of the following code? EXTREG := 1; _INTREG := 1; { “wait for clock!” }; [.. “start endless loop” | EXTREG := _INTREG + EXTREG; _INTREG := EXTREG; { “wait for clock!” } ] “end of loop”

1/1/ / faculty of Electrical Engineering eindhoven university of technology AL language: commands AL block gives commands like state controllers – same syntax, including paths and signal uses – numeric value parameters can be expressions STACK push: + ACCU); Local registers can also be given commands – these know ‘reset’, ‘inc’, ‘dec’ and ‘ressem’ – setting the semaphore is done on assignment

1/1/ / faculty of Electrical Engineering eindhoven university of technology AL language: test blocks Basically, same syntax as in state controllers – only one test expression, no state transitions Assigning test result to local register possible – test value taken from register, which can change: [ _LOCALREG := EXTREG | 0 _LOCALREG inc“if this is done…” | 1 EXTREG := 4“…then this too” ]; Breaking out of test block possible with ‘ >> ’ – from nested tests with ‘ >> 2 ’, ‘ >> 3’ etc.

1/1/ / faculty of Electrical Engineering eindhoven university of technology AL language: loops (1) Syntax is simple: [ “loop spec” | “body” ]; – the loop spec uses ‘..’ as body placeholder – the body is any valid sequence of statements While..do.. and do..until.. are very similar – while..do.. tests for non-zero before executing body [ _REG > 0.. | _REG dec. ]; “. = clock” – do..until.. executes body before testing for non-zero [.. _REG = 0 | _REG dec. ]; – both may assign test result to local register

1/1/ / faculty of Electrical Engineering eindhoven university of technology AL language: loops (2) Breaking out of a loop is done with ‘>>>’ An endless loop looks like this: [.. | “body” ]; – without a loop break, only at end of main routine! Counted loop example: [ _REG := | := 0 ]; – start and target values can both be expressions – counter increments/decrements towards target value – without assignment, counter is hidden – the only loop which can run without waiting for clock

1/1/ / faculty of Electrical Engineering eindhoven university of technology AL language: calls and returns local subroutine call: => _ReadParam; – does not take any simulation time global subroutine call: => ExecInterrupt; – waits for clock before executing actual call return from subroutine: <= – wait for clock in global subroutine and main routine – implicit return placed at end of each routine – may be nested in test blocks and/or loops – at end of main routine, AL block becomes ‘idle’

1/1/ / faculty of Electrical Engineering eindhoven university of technology AL language: wait statements (1) The simplest one: ‘wait here for the clock’ – replace ‘;’ separator by a period (easy to miss!) – use ‘empty wait statement’: ‘ {}; ’ Wait for more than one clock: ‘ { 2 | } ’ – value or expression specify additional clocks to wait The ‘wait expression’: wait and test – can be used instead of normal expression – can test asynchronous values (f.i. connectors) _ALURESULT := { ALU\\output }; – returns value as it was just before the clock

1/1/ / faculty of Electrical Engineering eindhoven university of technology AL language: wait statements (2) Wait for clock until value non-zero possible – basic form: { | STARTREG }; – ‘startup delay’, holds off testing a number of clocks: { _MINWAIT | NOTBUSYBIT }; – with ‘timeout’, returns after max. number of clocks: { | DATAVALID | _TOCLOCKS }; – combined: { 2 | TST | 2 }; “value at 3rd clk” – can be used in assignment, timeout returns zero value returned is value from just before the clock

1/1/ / faculty of Electrical Engineering eindhoven university of technology AL language: wait statements (3) Looks difficult, but is easy to remember... – value or expression before first ‘ | ’: number of clocks to wait before testing starts – expression after first ‘ | ’: the test expression which should return non-zero – value or expression after second ‘ | ’: number of clocks until timeout – if there are no vertical bars at all: just test the expression, no startup, no timeout – the test itself adds one clock to return the result

1/1/ / faculty of Electrical Engineering eindhoven university of technology AL blocks debugging environment One window does it all with four modes: – local variable definition, monitoring and editing – main, local and global (sub)routine editing/compiling – program execution tracing down to statement level – execution stack monitoring and editing More of these can be attached to one AL block – allows multiple aspects monitoring at the same time

1/1/ / faculty of Electrical Engineering eindhoven university of technology AL blocks single stepping Option switchable for trace and stack modes: Execute next statement Execute until wait statement Perform next clock step

1/1/ / faculty of Electrical Engineering eindhoven university of technology Conclusion AL blocks from abstraction level above RTL Easy to specify complex behaviour –With a high level ‘program flow’ –But close to hardware in operations and data storage Integrated within RTL environment –AL blocks communicate via RTL constructs –After AL-to-RTL conversion: same communication IDaSS RTL prepared for AL-to-RTL conversion! –FSM’s know subroutines, interrupts and ‘idle’ state

1/1/ / faculty of Electrical Engineering eindhoven university of technology AL blocks workshop Example files: – ‘alexmple.des’ shows all constructs in operation open register and trace windows, single step! – ‘al8048.des’: processor core in AL block Do-it-yourself: – try out the assignment (question) example – create a digital FIR filter: data samples and constant memories (signed!) sample memory shifts new sample each cycle result is sum over data[i] +*+ constant[i]