1. 1/1/ / faculty of Electrical Engineering eindhoven university of technology Architectures of Digital Information Systems Part 1: Interrupts and DMA dr.ir. A.C. Verschueren Eindhoven University of Technology Section of Digital Information Systems

2. 1/1/ / faculty of Electrical Engineering eindhoven university of technology What IS communication? For a computer to do any useful work, it must communicate with its surroundings 'Communication' consists out of two things 1)Information transfer 2)Synchronisation These may be present in variable amounts, from pure (continuous) information transfer to pure synchronisation First, clear a common misconception... no user interface  no communication

3. 1/1/ / faculty of Electrical Engineering eindhoven university of technology address 0 7 decoder addr ‘Memory mapped’ input/output Addresses in memory space are used to access the I/O ports with normal memory read/writes –More ports possible by extra address decoding input port output port 1 memory CPU inputoutput memory 4 'real' data addr read write 4..7 select 0 1

4. 1/1/ / faculty of Electrical Engineering eindhoven university of technology Separate input/output (address) space The CPU uses extra control signals (and special instructions) to access input and output ports –More ports possible by adding control signals or by using the address bus to encode port addresses CPU memory input output data read inread write addr out write

5. 1/1/ / faculty of Electrical Engineering eindhoven university of technology Ports and synchronisation Input ports transfer data to the processor data bus Output ports 'latch' (remember) the data provided by the processor between output accesses Synchronisation of data transfer can be done –Use separate output port bits as synchronisation signal –Use read/write/in/out signals for synchronisation –Receiving synchronisation signals via input port bits is very time consuming: they need continuous checking

6. 1/1/ / faculty of Electrical Engineering eindhoven university of technology Receiving synchronisation signals It is much better to let the synchronisation signal itself inform the CPU that it has become activated ! –Add hardware to the CPU which 'listens' to a synchronisation signal –When activity is detected, this hardware... 1)Stops whatever the CPU was doing 2)Handles the synchronisation signal by calling a subroutine –At return from this subroutine, the program which was running is continued as if nothing has happened This forms the basis of the 'interrupt' mechanism –The subroutine started by the hardware is called 'interrupt routine'

7. 1/1/ / faculty of Electrical Engineering eindhoven university of technology Basic interrupt hardware and operation An input pin on the CPU is checked at the end of handling each instruction –The PC is saved and a JUMP (to a specific address) is performed if this pin is found to be active –At the end of the interrupt routine, the PC must be restored to continue with the interrupted program –The interrupt routine should not modify storage locations (memory AND registers) used by this program …unless they form the communication medium between the interrupt routine and the program !

8. 1/1/ / faculty of Electrical Engineering eindhoven university of technology Saving & restoring PC and other registers Use separate register sets for the main program and the interrupt routines – Limited number of interrupts, no recursion possible + Extremely fast switching, interrupt 'tasks' possible Save register set in fixed memory locations – Much slower switching, no recursion possible + Simple hardware if most of work done in software Save register set on the stack – Still slow in switching + Recursion possible, can use existing hardware (for CALL, RET, PUSH, POP)

9. 1/1/ / faculty of Electrical Engineering eindhoven university of technology Where to start the interrupt routine ? At hardware-fixed locations in program memory – Very inflexible, number of interrupts limited + Relatively simple hardware External logic provides start address (input port) – Complex hardware outside the CPU + Can be very flexible, simple hardware in CPU Use a table in memory indexed by interrupt nr. – Special hardware in CPU (moderate complexity) + Reasonable flexibility, efficiency and speed

10. 1/1/ / faculty of Electrical Engineering eindhoven university of technology Importance of interrupts Not all interrupts are equally important 1)Interrupt routines may not be interrupted by less important ones –If a less important interrupt occurs, this must be remembered so that its routine can be started a.s.a.p. 2)Interrupt routines must be interruptable by more important ones Most CPU’s automatically disable ALL interrupts when an interrupt routine is started We need much ‘finer’ control than that !

11. 1/1/ / faculty of Electrical Engineering eindhoven university of technology Remembering, masking & prioritising Hardware should remember an interrupt’s occurrence until it is actually handled –May be part of I/O synchronisation hardware Must be possible to 'mask' (disable) interrupts individually –Software controlled mask bits via an output port –Mask bits can be controlled completely by hardware Hardware should 'prioritise' interrupts to select the most important non-masked one Possible, but very slow in software !

12. 1/1/ / faculty of Electrical Engineering eindhoven university of technology interrupt requests Interrupt controller devices The number of interrupts varies a lot (0.. >200) –Use separate interrupt controller devices to accomodate interrupt request receiver mask register & logic priority & selection logic vector generator vector request & vector transfer CPU interface 'interrupt handled’ enable / disable mode setting s vector setting s (I/O ports) ‘in service register’: routine started but not finished yet ‘interrupt request register’: requested but not started yet

13. 1/1/ / faculty of Electrical Engineering eindhoven university of technology Equally important interrupts Giving these fixed priorities leads to 'starvation' –The lowest priority never gets handled (or very slow) Solution: use 'rotating priority' within such a group 1 2 3 4 56 7 8 lowest priority! interrupt 4 handled 12 3 4 56 7 8 priority

14. 1/1/ / faculty of Electrical Engineering eindhoven university of technology ‘Cascading’ to get more interrupt inputs master controller interrupt request vector handshake vector interrupt interrupt inputs slave controller 1 slave controller N slave selection for vector generation Master should not disable slave input during interrupt Limited capabilities for rotating priorities only within slaves !

15. 1/1/ / faculty of Electrical Engineering eindhoven university of technology ‘Daisy chaining’ to get more interrupts Very slow: signals must pass through all controllers Inflexible: priority determined by placement in chain interrupt vector interrupt request controller 1 controller N interrupt inputs in out in out 'false' vector handshake No request: out  in Active request: out  ‘true’ Give vector if: out AND (NOT in)

16. 1/1/ / faculty of Electrical Engineering eindhoven university of technology The end of an interrupt routine Controllers need to know when a routine ends –To allow the next interrupt on the same input –To restore interrupt masks to their original status –To modify priorities in a rotating priority group This event is completely determined by software! –Use special RET instruction, 'visible' to controllers –Inform the interrupt controllers with I/O operations

17. 1/1/ / faculty of Electrical Engineering eindhoven university of technology ‘Traps’: interrupts from within the CPU Generated when instructions encounter an error –Arithmetic errors, f.i.:overflow, divide by zero These traps can be seen as the hardware basis for 'exceptions' –Hardware errors, f.i.: memory fault, accessed device does not respond Traps and interrupts have some small differences –During trap handling, most interrupts remain enabled –A trap handler is an extension of the running program –The trapped instruction will in general be re-started following the trap handling routine This is sometimes very difficult !

18. 1/1/ / faculty of Electrical Engineering eindhoven university of technology request grant CPU I/O HW Reducing I/O handling time even further Interrupts still require a lot of software (= time!) to move data between memory and a port –Save time by allowing I/O hardware to access memory directly, without assistance of the CPU This is called 'Direct Memory Access' (DMA) CPU has bus memory DMArequest DMAgrant read write data address CPU releases I/O HW has bus CPU takes bus back

19. 1/1/ / faculty of Electrical Engineering eindhoven university of technology The ‘intelligence’ of DMA DMA can be used to create and/or read complex data structures without bothering the CPU –This requires a lot of 'intelligence' in the I/O hardware –Still requires an interrupt to signal the main program Concurrent I/O needs multiple DMA 'channels’ –Same functionality needed as for handling multiple interrupts (remembering, masking and prioritising) But this time, it has to be all in hardware !

20. 1/1/ / faculty of Electrical Engineering eindhoven university of technology Memory Using a separate DMA controller DMA controller can handle multiple I/O requests –Requires the same functionality as multiple interrupts (masking, priorities...) CPU I/O DMA control in out read write address DMArequest DMAgrant IOrequest IOreq in out read write data address in out data read write data address Simple interface !

21. 1/1/ / faculty of Electrical Engineering eindhoven university of technology Types of DMA controllers (1) Direct processor controlled DMA (generation 1) –Transfers one data block at a time –Requires main processor support for each data block Instruction list controlled DMA (generation 2) –Transfers multiple data blocks autonomously –Controlled by command (linked) list in memory

22. 1/1/ / faculty of Electrical Engineering eindhoven university of technology Types of DMA controllers (2) DMA co-processors (generation 3) –Handle I/O tasks including transfer of data blocks –Run their own programs (stored in DMA memory), controlled by 'messages' in main memory main processor DMA co-processor I/O hardware main memory DMA memory