CSET 4650 Field Programmable Logic Devices Dan Solarek Introduction to PALs Programmable Array Logic

2 Programmable Array Logic (PAL) Developed by John Birkner & Hua-Thye Chua Monolithic Memories, Inc Used to implement functions in Boolean equation form (Recall PROM used tabular form) More efficient use of IC real estate Developers continued into FPGAs Co-founders of Quicklogic

3 Programmable Array Logic (PAL) AND array inputs are programmable OR array connections are fixed The output of each AND gate is permanently connected to an OR gate Product terms cannot be shared by OR gates Simplified PAL block diagram: Fixed Connections

4 PAL Block Diagram A more realistic block diagram of a PAL would show multiple inputs and outputs

5 PAL Architecture: Simplified Inputs are available in both true and inverted form Multiple input AND gates Each OR gate has a specific number of product terms as fixed inputs Outputs from OR gates

6 Using PALs: An Example P 1 P 2 x 1 x 2 x 3 P 3 P 4 Implement the following: AND plane

7 Using PALs: An Example P 1 P 2 x 1 x 2 x 3 P 3 P 4 AND plane P4P4 P3P3 P2P2 P1P1 f1f1 f2f2

8 PAL Architecture: More Realistic Six (6) inputs are available in both true and inverted form Twelve (12) input AND gates Each OR gate has a four (4) product terms as fixed inputs Four (4) outputs

9 PAL Architecture: More Realistic The fact that the AND array is programmable makes it possible for these devices to have many inputs The fact that the OR array is fixed makes the devices small (which means less expensive) and fast

10 PAL Architecture An actual PAL device PAL16L8 32 input AND gates up to 8 output functions See Figure 7-24 in the Sandige book

11 PAL Outputs Can Be Latched Typical PALs have: from 10 to 20 inputs from 2 to 10 outputs from 2 to 8 AND gates driving each OR gate often include D flip-flops f 1 To AND plane DQ Clock Select Enable Flip-flop MUX output is “fed back” to the AND plane.

12 Understanding the PAL Diagram A portion of the Realistic PAL diagram shown earlier

13 Understanding the Diagram Horizontal Lines indicate a product term. Vertical lines provide True and Complemented forms of external inputs. Although product terms appear to have only one input, it actually has 2*n inputs, for n external inputs. DJ P

14 PAL Product Terms This looks like an AND gate with one input. It is actually many more: B B’ A A’ C C’ H’ H Drawn with a single line (above) to save space. B B’A A’ C C’ D D’ I I’ J J’ E E’ F F’ K K’GG’H H’ P

15 D J P Fuse Points A cross over of a Vertical input line and a horizontal product term line is a FUSE LOCATION. When the PAL is in its blank or erased state, all FUSES are connected. This means that each product term implements the equation: ( A A’ B B’ C C’……. KK’) which will be ‘0’! This means that the output will be high!

16 DJ P PAL Programming To program, we will BLOW most of the fuses (break the vertical/horizontal crossover connection). To indicate a logic function, will use an ‘ X ‘ over a fuse will be kept INTACT. Will mark intact fuse location When a fuse is blown, that product term input acts as a permanent logic ‘1’ so that the input no longer effects the product term.

17 An Example: P’ = D + J’ When implementing an equation, sometimes will not want to use all available product terms. If ALL fuses along product term are left intact, then product term value will be ‘0’ and will not affect equation. Mark unused AND gates by placing an X over them as shown. D J P

18 Example Product Term AC’H’ The connections will be: B B’A A’ C C’ D D’I I’ J J’ E E’ F F’ K K’GG’H H’ 1 1 A 1 1 C’ H’ 1 Fuse blown Fuse intact Fuse blown Fuse intact Fuse blown Fuse intact Actually, fuses are not ‘blown’ in eraseable PLDs - the connection is broken in a non- destructive way. P P

19 Another Example A B C D G H I J P P’ = A’BGH’ + CD’ + HIJ + BG’H

20 Alternative PAL Diagrams Implements sum-of- products expressions Four external inputs (and complements) Feedback path from output F 1 Product term connections made via fuses

21 Implementing a Function Consider implementing the following expression: I 1 I 2 I 3 + I 2 ’ I 3 ’ I 4 + I 1 I 4 = F 1 Note that only functions of up to three product terms can be implemented larger functions need to be chained together via the feedback path x x x x x x x x

22 10 primary inputs 8 outputs, with 7 AND gates per output 1 AND used for 3-state enable 6 outputs available as inputs more inputs, at expense of outputs Note inversion on outputs output is complement of sum-of- products newer PALs have selectable inversion Example 7-12 from Sandige Figure 7-24

23 PAL Output Macrocells 4 to 1 MUX 00 = registered active low 01 = registered active high 10 = comb. active low 11 = comb. active high 2 to 1 MUX Output feedback External input

24 PAL Output Macrocells Registered mode

25 PAL Output Macrocells combinational mode