Algorithmic (Cyclic) ADC

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Presentation transcript:

Algorithmic (Cyclic) ADC Data Converters Algorithmic ADC Professor Y. Chiu EECT 7327 Fall 2014 Algorithmic (Cyclic) ADC

Algorithmic (Cyclic) ADC Data Converters Algorithmic ADC Professor Y. Chiu EECT 7327 Fall 2014 Algorithmic (Cyclic) ADC Sample mode Input is sampled first, then circulates in the loop for N clock cycles Conversion takes N cycles with one bit resolved in each Tclk

Modified Binary Search Data Converters Algorithmic ADC Professor Y. Chiu EECT 7327 Fall 2014 Modified Binary Search Conversion mode If VX < VFS/2, then bj = 0, and Vo = 2*VX If VX > VFS/2, then bj = 1, and Vo = 2*(VX-VFS/2) Vo is called conversion “residue”

Modified Binary Search Data Converters Algorithmic ADC Professor Y. Chiu EECT 7327 Fall 2014 Modified Binary Search Constant threshold (VFS/2) is used for each comparison Residue experiences 2X gain each time it circulates the loop

Loop Transfer Function Data Converters Algorithmic ADC Professor Y. Chiu EECT 7327 Fall 2014 Loop Transfer Function  Comparison → if VX < VFS/2, then bj = 0; otherwise, bj = 1 Residue generation → Vo = 2*(VX - bj*VFS/2)

Data Converters Algorithmic ADC Professor Y. Chiu EECT 7327 Fall 2014 Algorithmic ADC Hardware-efficient, but relatively low conversion speed (bit-per-step) Modified binary search algorithm Loop-gain (2X) requires the use of a residue amplifier, but greatly simplifies the DAC → 1-bit, inherently linear (why?) Residue gets amplified in each circulation; the gain accumulated makes the later conversion steps insensitive to circuit noise and distortion Conversion errors (residue error due to comparator offset and/or loop-gain non-idealities) made in earlier conversion cycles also get amplified again and again – overall accuracy is usually limited by the MSB conversion step Redundancy is often employed to tolerate comparator/loop offsets Trimming/calibration/ratio-independent techniques are often used to treat loop-gain error, nonlinearity, etc.

Data Converters Algorithmic ADC Professor Y. Chiu EECT 7327 Fall 2014 Offset and Redundancy

Vo = 2*(Vi - bj*VFS/2) → Vi = bj*VFS/2 + Vo/2 Data Converters Algorithmic ADC Professor Y. Chiu EECT 7327 Fall 2014 Offset Errors Ideal RA offset CMP offset Vo = 2*(Vi - bj*VFS/2) → Vi = bj*VFS/2 + Vo/2

Redundancy (DEC, RSD) 1 CMP 3 CMPs Data Converters Algorithmic ADC Professor Y. Chiu EECT 7327 Fall 2014 Redundancy (DEC, RSD) 1 CMP 3 CMPs

Loop Transfer Function Data Converters Algorithmic ADC Professor Y. Chiu EECT 7327 Fall 2014 Loop Transfer Function Original w/ Redundancy Subtraction/addition both required to compute final sum 4-level (2-bit) DAC required instead of 2-level (1-bit) DAC

Data Converters Algorithmic ADC Professor Y. Chiu EECT 7327 Fall 2014 Comparator Offset Max tolerance of comparator offset is ±VFS/4 → simple comparators Similar tolerance also applies to RA offset Key to understand digital redundancy:

Modified 1-Bit Architecture Data Converters Algorithmic ADC Professor Y. Chiu EECT 7327 Fall 2014 Modified 1-Bit Architecture 1-b/s RA transfer curve w/ no redundancy One extra CMP added at VR/2

From 1-Bit to 1.5-Bit Architecture Data Converters Algorithmic ADC Professor Y. Chiu EECT 7327 Fall 2014 From 1-Bit to 1.5-Bit Architecture A systematic offset –VR/4 introduced to both CMPs A 2X scaling is performed on all output bits

Can this technique be applied to SA ADC? Data Converters Algorithmic ADC Professor Y. Chiu EECT 7327 Fall 2014 The 1.5-Bit Architecture 3 decision levels → ENOB = log23 = 1.58 Max tolerance of comparator offset is ±VR/4 An implementation of the Sweeny-Robertson-Tocher (SRT) division principle The conversion accuracy solely relies on the loop-gain error, i.e., the gain error and nonlinearity A 3-level DAC is required Can this technique be applied to SA ADC?

The Multiplier DAC (MDAC) Data Converters Algorithmic ADC Professor Y. Chiu EECT 7327 Fall 2014 The Multiplier DAC (MDAC) 2X gain + 3-level DAC + subtraction all integrated A 3-level DAC is perfectly linear in fully-differential form Can be generalized to n.5-b/stage architectures

A Linear 3-Level DAC b = 0 b = 1 b = 2 Data Converters Algorithmic ADC Professor Y. Chiu EECT 7327 Fall 2014 A Linear 3-Level DAC b = 0 b = 1 b = 2

Alternative 1.5-Bit Architecture Data Converters Algorithmic ADC Professor Y. Chiu EECT 7327 Fall 2014 Alternative 1.5-Bit Architecture How does this work? Ref: E. G. Soenen and R. L. Geiger, “An architecture and an algorithm for fully digital correction of monolithic pipelined ADC’s,” IEEE Trans. on Circuits and Systems II, vol. 42, issue 3, pp. 143-153, 1995.

Error Mechanisms of RA Capacitor mismatch Data Converters Algorithmic ADC Professor Y. Chiu EECT 7327 Fall 2014 Error Mechanisms of RA Capacitor mismatch Op-amp finite-gain error and nonlinearity Charge injection and clock feedthrough (S/H) Finite circuit bandwidth

RA Gain Error and Nonlinearity Data Converters Algorithmic ADC Professor Y. Chiu EECT 7327 Fall 2014 RA Gain Error and Nonlinearity Raw accuracy is usually limited to 10-12 bits w/o error correction

Static Gain-Error Correction Data Converters Algorithmic ADC Professor Y. Chiu EECT 7327 Fall 2014 Static Gain-Error Correction Analog-domain method: Digital-domain method: Do we need to correct for kd2 error?

RA Gain Trimming C1/C2 = 1 nominally Data Converters Algorithmic ADC Professor Y. Chiu EECT 7327 Fall 2014 RA Gain Trimming C1/C2 = 1 nominally Precise gain-of-two is achieved by adjustment of the trim array Finite-gain error of op-amp is also compensated (not nonlinearity)

Split-Array Trimming DAC Data Converters Algorithmic ADC Professor Y. Chiu EECT 7327 Fall 2014 Split-Array Trimming DAC 8-bit gain 1-bit sign Successive approximation utilized to find the correct gain setting Coupling cap is slightly increased to ensure segmental overlap

Digital Radix Correction Data Converters Algorithmic ADC Professor Y. Chiu EECT 7327 Fall 2014 Digital Radix Correction Unroll this:

Data Converters Algorithmic ADC Professor Y. Chiu EECT 7327 Fall 2014 References P. W. Li, M. J. Chin, P. R. Gray, and R. Castello, JSSC, pp. 828-836, issue 6, 1984. C. Shih and P. R. Gray, JSSC, pp. 544-554, issue 4, 1986. H. Ohara et al., JSSC, pp. 930-938, issue 6, 1987. H. Onodera, T. Tateishi, and K. Tamaru, JSSC, pp. 152-158, issue 1, 1988. S. H. Lewis et al., JSSC, pp. 351-358, issue 3, 1992. B. Ginetti et al., JSSC, pp. 957-964, issue 7, 1992. H.-S. Lee, JSSC, pp. 509-515, issue 4, 1994. S.-Y. Chin and C.-Y. Wu, JSSC, pp. 1201-1207, issue 8, 1996. E. G. Soenen and R. L. Geiger, TCAS2, pp. 143-153, issue 3, 1995. I. E. Opris, L. D. Lewicki, and B. C. Wong, JSSC, pp. 1898-1903, issue 12, 1998. O. E. Erdogan, P. J. Hurst, and S. H. Lewis, JSSC, pp. 1812-1820, issue 12, 1999.