1. – 1 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 Interpolation

2. – 2 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 Uniformly spaced zero-crossings in flash ADCs Ref: R. van de Grift, I. W. J. M. Rutten, and M. van der Veen, "An 8-bit video ADC incorporating folding and interpolation techniques," IEEE Journal of Solid-State Circuits, vol. 22, pp. 944-953, issue 6, 1987.

3. Resistive Interpolation – 3 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 Intermediate zero-crossings are recovered by interpolation. DNL is improved by voltage interpolation. Requires overlapped linear regions b/t adjacent preamps.

4. Interpolation Nonlinearity (I) – 4 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 Nonlinear TF of preamps cause errors in the interpolated zero-crossings. Interpolation nonlinearity directly translates into DNL and INL. Impedance mismatch due to interpolation also causes dynamic errors.

5. Interpolation Nonlinearity (II) – 5 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 Ref: R. J. van de Plassche and P. Baltus, "An 8-bit 100-MHz full-Nyquist analog-to- digital converter," IEEE Journal of Solid-State Circuits, vol. 23, pp. 1334-1344, issue 6, 1988. Interpolation factor of 4 Latch input bandwidth equalized Critical if input SHA is not used Nonlinear interpolation errors remain

6. Interpolation Nonlinearity (III) – 6 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 Ref: P. Vorenkamp and R. Roovers, "A 12-b, 60-MSample/s cascaded folding and interpolating ADC," IEEE Journal of Solid-State Circuits, vol. 32, pp. 1876-1886, issue 12, 1997. Resistive mesh network improves impedance matching at latch input. 2X interpolation avoids the interpolation error.

7. Capacitive Interpolation – 7 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 K. Kusumoto, JSSC, Dec. 1993

8. Current Interpolation – 8 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 Less accurate then voltage interpolation due to mismatch of current mirrors Ref: M. Steyaert, R. Roovers, and J. Craninckx, "100 MHz 8 bit CMOS interpolating A/D converter," in Proceedings of IEEE Custom Integrated Circuits Conference, 1993, pp. 28.1.1-28.1.4.

9. Features of Interpolation – 9 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 Reduces the total number of preamps by the interpolation factor. Total number of latches stay the same. Reduces the total input capacitance (larger input BW). More area- and power-efficient than straight flash ADC. Voltage interpolation improves DNL. Loading of interpolation network decreases the preamp gain/BW. Subject to preamp nonlinearities.

10. – 10 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 Folding

11. Inefficiency of Flash ADC – 11 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 Only comparators in the vicinity of V in are active at a time → low efficiency.

12. Segmented Quantization – 12 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 Analog pre-processing divides V in into 2 M uniformly-spaced segments. Segment indicator (M bits) Fine quantization (N-M) bits

13. Signal Folding – 13 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 Analog pre-processing → folding amplifier Folding factor (F) is equal to the number of folded segments. Segment indicator (log 2 (F) bits) Fine quantization N-log 2 (F) bits

14. Folding ADC Architecture – 14 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 The fine ADC performs amplitude quantization on the folded signal. The coarse ADC differentiates which segment V in resides in. F = 8

15. Folding Amplifier – 15 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 F = 3

16. Folding Amplifier – 16 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 F = 3 Zero-crossings are still precise!

17. Zero-Crossing Detection – 17 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 Only detect zero-crossings instead of fine amplitude quantization → insensitive to folder nonlinearities. P parallel folding amplifiers are required. F = 3, P = 4

18. Offset Parallel Folding – 18 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 Total # of zero-crossings = Total # of preamps = P*F Parallel folding saves the # of comparators, but not the # of preamps → still large C in. F = 3, P = 4

19. Signal Folding – 19 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 Pros Folding reduces the comparator number by the folding factor F, while the number of preamps remains the same. Cons Multiple differential pairs in the folder increases the output loading. “Frequency multiplication” at the folder output.

20. Frequency Multiplication – 20 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 CT vs. DT

21. Folding + Interpolation – 21 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 Cross-connect P & N sides at the endpoints 

22. “Rounding” Problem – 22 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 Large F results in signal “rounding”, causing gain and swing loss. Max. folding factor is limited by V ov of folder and supply voltage. F = 3 F = 9

23. Folding vs. Interpolation – 23 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 Folding Folding works better with non-overlapped active regions between adjacent folders. Large V ov (for high speed) of folders and low supply voltage limit the max. achievable F. Interpolation Works better with closely spaced overlapped active region between adjacent folding signals. Observation Small F and large P (parallel folders) will help both folding and interpolation, but introduces large C in – approaching flash… What else can we do?

24. Cascaded Folding – 24 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 Ideal: A large folding factor F can be developed successively. Small F in the 1 st -stage folder → large V ov, less capacitive loading, and less frequency multiplication effect. F = 3 F = 9 

25. Cascaded Folder Architecture (II) – 25 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 Simple differential pair-based folding amplifiers Only works with odd P, compatible with low supply voltage. F = ?

26. Cascaded Folder Architecture (I) – 26 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 Gilbert four-quadrant multiplier based folding amplifier Only works with even P, requires a lot of headroom F = ?

27. Mechanical Model of Cascaded Folding – 27 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 Bult (JSSC’97)

28. Distributed Preamplification – 28 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 Large signal gain developed gradually along the signal path → from “soft” to “hard” decision Gain

29. Useful Formulas – 29 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 Assuming a two-stage cascaded folding & interpolating ADC, F 1 = 1 st -stage folding factor, F 2 = 2 nd -stage folding factor, P = # of offset parallel folders, I = total interpolation factor, then, Total # of decision level = P*F 1 *I ADC Resolution = Log 2 (P*F 1 *I) Total # of fine comp = P*I/F 2 Total # of coarse comp = P*F 1 or P+F 1 ? where, usually P = F 2 holds.

30. Circular Thermometer Code – 30 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 Very tight coarse comparator offset requirement (<1/2 LSB) Aperture delay b/t coarse and fine worsens the problem. F = 4

31. Coarse-Fine Sync (Bit Alignment) – 31 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 “Coarse” fold indicator with offset thresholds combined with the output of fine comparator A precisely determines which fold V in resides in. Large tolerance on coarse comparator offset and aperture delay errors

32. Useful Formulas – 32 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 Assuming a two-stage cascaded folding & interpolating ADC, F 1 = 1 st -stage folding factor, F 2 = 2 nd -stage folding factor, P = # of offset parallel folders (P>F 2 ), I = total interpolation factor, then total # of decision level = P*F 1 *I, ADC Resolution = Log 2 (P*F 1 *I), total # of preamps in 1 st folder = P*F 1, total # of preamps in 2 nd folder = P, total # of fine comparators = P*I/F 2, total # of coarse comparators = F 1 *F 2, F 1 +F 2, or F 1 +P?

33. Cascaded Offset Bit Alignment (I) – 33 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 F 1 coarse comparators at input and P coarse comparators at 1 st -stage folder outputs resolve F 1 *P (>F 1 *F 2 ) folds. One fine comparator output is utilized to perform offset bit alignment.

34. Cascaded Offset Bit Alignment (II) – 34 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 Two-step offset bit alignment – large offset tolerance on F 1 coarse comparators and medium tolerance on P comparators.

35. References – 35 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 1.R. J. van De Plassche et al., JSSC, vol. 14, pp. 938, issue 6, 1979. 2.R. E. J. van De Grift et al., JSSC, vol. 19, pp. 374-378, issue 3, 1984. 3.R. E. J. van De Grift et al., JSSC, vol. 22, pp. 944-953, issue 6, 1987. 4.R. J. van de Plassche et al., JSSC, vol. 23, pp. 1334-1344, issue 6, 1988. 5.J. van Valburg et al., JSSC, vol. 27, pp. 1662-1666, issue 12, 1992. 6.B. Nauta et al., JSSC, vol. 30, pp. 1302-1308, issue 12, 1995. 7.A. G. W. Venes et al., JSSC, vol. 31, pp. 1846-1853, issue 12, 1996. 8.M. P. Flynn et al., JSSC, vol. 31, pp. 1248-1257, issue 9, 1996. 9.P. Vorenkamp et al., JSSC, vol. 32, pp. 1876-1886, issue 12, 1997. 10.K. Bult et al., JSSC, vol. 32, pp. 1887-1895, issue 12, 1997. 11.M. P. Flynn et al., JSSC, vol. 33, pp. 1932-1938, issue 12, 1998. 12.M.-J. Choe et al., VLSI, 1999, pp. 81-82. 13.R. C. Taft et al., JSSC, vol. 39, pp. 2107, issue 12, 2004.