An 8-GHz Continuous-Time  ADC in an InP-based DHBT Technology Sundararajan Krishnan*, Dennis Scott, Miguel Urteaga, Zachary Griffith, Yun Wei, Mattias Dahlstrom, Navin Parthasarathy, Mark Rodwell University of California, Santa Barbara * Now with Texas Instruments, India;

 -  ADC: Introduction High resolution using over-sampling and noise-shaping Negative feedback used to shape spectral char. of quantization noise Order of linear system is order of ADC Design can be in discrete-time(DT) or continuous-time(CT) InP-based HBTs have shown high cutoff-frequencies; hence, high clock-rates possible No good switches, though. Hence, design is CT

InP/InGaAs/InP Mesa DHBT Technology Discussion - Device Results narrow 1.7  m base mesa, 0.7  m emitter J kirk = 2e5 A/cm Vce = 0.7 V f  = 200 GHz; f max =205 GHz  = 35; BV CEO = 6 V E B C

IC wiring environment Interconnect cross-sectiontop view after plating ground-plane BCB ground plane resistorsmetal1SiNmetal2 Thin-film-dielectric (5  m BCB) micro-strip wiring Reduced ground via inductance, Minimal line - line coupling 8  m line gives controlled 50  impedance

 -  ADC: Introduction Filter is second-order gm-C. Zero realized with a series R M-S-S latch is the 1- bit quantizer. DAC is RTZ, and is realized as a current- steering switch 1-bit quantizer Additional stage of regeneration used in the quantizer to reduce meta-stability errors DAC is RTZ to minimize SNR-degradation due to excess delay from the additional stage of regeneration

Divider: test structure for the Latch f clk = 87 GHz Latch configured as a static frequency divider shows maximum f clk of 87 GHz; Power consumed in divider is 700mW Even at such high switching speeds, meta-stability is a serious concern

Effect of M-S-S latch on SNR Additional stage of regeneration necessary to minimise metastability errors Excess delay introduced by the additional stage alters quantizer input, output spectrum and degrades SNR Loss in SNR fully recovered by moving centroid of DAC to original position CLK I dac M-S latch I dac M-S-S latch t t t M-S S DAC addl. stage of regeneration V 

RTZ DAC : A way to recover SNR RTZ DAC pushes centroid forward by T clk /4 Zeroes of the loop can be adjusted to compensate for the rest of the delay (T clk /4) CLK I dac M-S latch t t I dac Ideal location RTZ DAC t t I dac M-S-S latch RTZ DAC t

Final designs (10 GHz clock) Integrator-1 Integrator-2 MasterSlave DAC NRZ DAC RTZ DAC

Analog measurements – Spectrum Analyzer RTZ-DAC-based ADC has higher resolution (as expected) Noise-floor of RTZ-DAC-based ADC evens out at low frequencies ( < 125 MHz); digital acquisition needed to measure dynamic range (DR) at lower end of spectrum accurately Both ADCs consume ~1.5W of power (mostly in the latch) 10 GHz clock-rate

Measurement by Digital Acquistion Logic Analyzer cannot read 8 Gbps; demux to 500 Mbps Signal reconstructed in software FFT performed in Math; no dynamic-range problems In software

One-tone measurements Output power referenced to power in fundamental for a square- wave at that frequency Performance not ideal for over sampling ratios >=32 Meta-stability and latch latency dominate at lower end of spectrum f in = 62.5 MHz; P in = 3 dBmf in = 250 MHz; P in = 3 dBm Clock-rate = 8 GHz; FFT bin size = 61 kHz

SNR and # of bits of resolution Noise power measured at upper band edgeNoise power integrated to signal frequency For an equivalent Nyquist-rate ADC, SNR and effective # of bits of resolution, ENOB, are related by ENOB = (SNR-1.76)/6.02

Effect of latch latency on output spectrum Clock signal to RTZ-DAC delayed (relative to comparator) to avoid glitches in DAC pulse If delay not optimum (probably the case), output spectrum not ideal Spurious glitches if clock not delayed

Effect of comparator speed on noise-shaping Comparator speed increased by increasing bias current With a slower comparator, output spectrum is dominated by metastability at frequencies < 150 MHz M-S latches 10:1 faster than clock rate for low metastability

Two-tone measurements Integrator bias current >> RTZ-DAC current to achieve linearity in the input stage > 80 dBc suppression of intermodulation at lower bias Same voltage source for integrator, DAC and comparator; DAC current increases much faster than Integrator bias current; Intermodulation suppression degrades with increasing bias Slower comparator – lower biasFaster comparator – higher bias FFT bin size = 61 kHz

Conclusions Demonstrated a 2 nd order, continuous-time  -  ADC clocked at 8 GHz in a 200GHz f , f max InP-based technology ADC measured using both Analog and Digital acquisition techniques ADC has 48dB SNR at an OSR of 32. (Ideal performance is 3dB higher) ADC performance limited by meta-stability errors and latch latency at the lower end of the spectrum > 75dBc suppression of intermodulation-products observed