Presentation on theme: "D. Wei, Y. Huang, B. Garlepp and J. Hein"— Presentation transcript:
1 A Monolithic Low-Bandwidth Jitter-Cleaning PLL with Hitless Switching for SONET/SDH Clock Generation D. Wei, Y. Huang, B. Garlepp and J. HeinSilicon Laboratories Inc., Austin, TexasPresented in ISSCC, Feb, 2006
2 New Breed of Analog Designers: digAnalog Requirement for analog interface is higher and higher (i.e. multimedia application), yet technology advancement shies away from the analog performanceExample: 1/f noise, gate leakage, device non-idealityDigital signal processing is so powerful today!Deep sub-micron CMOSMore computation power for limited-size areaIntegration is the trendConsumer electronics require compactnessDelicate process means higher ASP and lower revenuesQ: can we enhance the “analog” performance by the power of “digital”?
3 Insights of Analog-to-digital Interface Go against the technology trend
4 Insights of Analog-to-digital Interface (con’t) Demand faster technology but with less accuracy!
5 digAnalog Design Rules Good understanding of the system requirements“To dig or not to dig, that is the question”Pick the right “candidate” (voltage, current, flux, phase, …) to processWhat defines your “signal”?Faster technology available (and cheap!)signal bandwidth vs. sampling clock
12 Digital Implementation of Hitless Switching (1) PLL LBW < 12KHzPFD SDADC fs = 311MHz
13 PFD ADC and Auto-zero Loop “shift” the offset DAC valueAZ bandwidth ~ 100KHzD avoids the DAC overflowLoop Bandwidth < 12KHz vs. SDADC fs = 311MHz SNR > 22bitsPFD full scale = 6.42ns Offset DAC LSB ~ 100ps
14 What if Frequency Error Is Present? <8FSPDDfoffset,max =FSPDmodulus (k=0~7)Dfout,1,2 = (fA-fB) - (foffsetA-foffsetB) – k (0.5 2FSPD)2FSPD: Phase Detector Full-scale (6.42ns)
15 Digital Implementation of Hitless Switching (2) Each swallow: TD = 8Tvco
16 Phase Transient Measurement Setup adjustable DfLinear phase detector “demodulates” the DUT output phaseLOS (loss-of-signal) on clkB triggers the oscilloscope
17 Measured Phase Transient During Reference-switching Wandering due to LOSLoop relocks the phase116psPD outresidual Df = 35psLOSB trigger the switchingInitial Df = 180 (~25ns)LOSBMode: Auto-switching (LOS triggers the switching)
18 Removing the External Loop Filter DSP implementation replaces the bulky external loop filters (LF)Less Bill-of-Materials (BOM)Avoid excess noise-coupling at post-LF nodes
19 DSP-based Loop Filter Implementation Gain ratio controls LBW and peakingNo external loop filter components needed
20 PLL Bandwidth and Peaking Control Feedforward (F)PFD ADCIntegration (I)feedforward bits addedInput bits accumulatedvaractor codesReduced by SD (rounding)KF ~ LBW / (KPD x Kv)KI ~ (LBW)2 x (d-1) / (KPD x Kv)For Type-II PLL with low-peaking (d<0.1dB),
21 Connecting the Loop Filter to Varactors 2nd-order SD generates varactor cntl. voltageDAC expander reduces the analog hardware cost by 16x
26 Discrete Solution vs. Integrated Solution 50mmdiscrete solutionhybrid solution23mm11mmpresented solutionNo external loop filters are required.dramatically simplifies the line card design!
27 PLL Characteristics Measurement 101001K10K100K1M10MFrequency (Hz)L(f) (dBc/Hz)-20-40-60-80-100-120-140-160Phase LBW=800Hz622.08MHz Output-97dBc/Hz@10KHz-142dBc/Hz@1MHzJitter GenerationFrequency (Hz)1001K10K-2-4-6-8-10-12-14-16Loop Transfer (dB)800Hz1600Hz3200Hz6400HzJitter Transfer219.44Mhz Input622.08MHz OutputMeasured integrated jitter:OC48 band 0.69psOC192 band 0.26psMeasured peaking: < 0.1dB
28 Performance Summary 0.25m-CMOS 3.5mm by 5.1mm 11 X 11 CBGA 350mW Technology0.25m-CMOSDie Size3.5mm by 5.1mmPackage11 X 11 CBGAVdd=3.3V350mWSupported PLL Bandwidth (LBW)800Hz, 1600Hz, 3200Hz, 6400HzLoop Transfer Peaking<0.1dBDuring Reference BW=800HzMaximum Output Phase Step200psMaximum Output Phase Slope (MTIE: <61.08 ns/ms for 3/4E)4.5 ns/msJitter BW=800HzOC-48 band (12KHz ~ 20MHz)0.8ps (WC)OC-192 band (50KHz ~ 80MHz)0.4ps (WC)
29 ConclusionDigital “hitless” clock-switching is demonstrated, enabling the on-chip implementation for SONET/SDH clock management.Loop components are digitally implemented, which minimizes the external noise coupling and also has the good control over loop characteristics.Concise digital implementation of digital varactors simplifies the hardware implementation, and enhances the VCO performance, enabling the “jitter-cleaning” to the PLL input clocks.