Beam Secondary Shower Acquisition System: Analogue FE installation schedule and Digital FE Status BE-BI-BL Jose Luis Sirvent Blasco 2 Jose Luis Sirvent Blasco PhD. Student STUDENT MEETING 16/03/2015

1. Analogue Front-End: Installation for testing purposes Location : SPS (BA50 / RA1705) SPS Schedule: Technical Stop 19/03/2015  Trip for Observation Technical Stop 08/04/2015  Analogue Front-End installation Technical Stop 26/09/2015  Digital Front-End installation ?? BE-BI-BL Jose Luis Sirvent Blasco 3 BWSD51731 Linear Wire Scanner S Start: m BWSRE51740: Rotative WS Prototype S Start: m 6.7m SLAC Collimator Potential location??

BE-BI-BL Jose Luis Sirvent Blasco 4 1. Analogue Front-End: The pCVD Front-End (BLM – Like): cables needed Power + 12V (BNC-CB50) Power - 12V (BNC-CB50) HG Signal (Type N - CK50) LG Signal (Type N - CK50) pCVD High Voltage (HVPF-CBH50) Pieces and Equipment provided by Ewald Effinger

BE-BI-BL Jose Luis Sirvent Blasco 5 1. Analogue Front-End: Are these cables on the BWSRE51740 location?? I’d say yes, and 5m seems enough to reach the potential location

Adaptation of: EDA HPA-High Frequency PMT Amplifier BoxEDA HPA-High Frequency PMT Amplifier Box By J. Koopman 08/10/2007 Used on BWS PMT as far as I know there have not been major issues with this amplif and radiation. BE-BI-BL Jose Luis Sirvent Blasco 6 2. The pCVD amplifier: A look in detail Input Protection Limited output voltage Stability and Low pass filter Relay for Test Lamp

Something extremely simple 1x THS3001 1x Resistor 1 K ohm 2x Resistor 51 ohm 2x Decoupling Caps 100nF 2x Decoupling Caps 1uF 2x SMA Connectors (In/Out) 2x LEMO Connectors (Power +/- 12V) Impedance matched In/Out Inverter configuration May be a good idea to use non-inverter configuration HG and LG channels with same polarity BE-BI-BL Jose Luis Sirvent Blasco 7 2. The pCVD amplifier: What is inside then?

BE-BI-BL Jose Luis Sirvent Blasco 8 2. The pCVD amplifier: What is inside then?

BE-BI-BL Jose Luis Sirvent Blasco 9 2. The pCVD amplifier: Some performance tests (1. Square wave 20Mhz) INPUT OUTPUT

BE-BI-BL Jose Luis Sirvent Blasco The pCVD amplifier: Some performance tests (2. Short Pulses 5ns width) INPUT OUTPUT

BE-BI-BL Jose Luis Sirvent Blasco The pCVD amplifier: Some performance tests (3. Charge Signal: AC coupled Square 10pF) INPUT OUTPUT Reflections due to decoupling cap (Impedance mismatching) Which are present also in the input: not amplifier’s fault

BE-BI-BL Jose Luis Sirvent Blasco Expected charge on pCVD for BWSRE51740 : Rough calculations based on A.Lecker simulations 2m from IP) # of interacting particles 2m (Gy) Charge in detector (C) Generated Current (A) Estimated signal magnitude 2m): *Roughly these values are divided by 5m

BE-BI-BL Jose Luis Sirvent Blasco Expected charge on pCVD for BWSRE51740 : Rough calculations based on A.Lecker simulations 2m from IP) # of interacting particles 2m (Gy) Charge in detector (C) Generated Current (A) Estimated signal magnitude 2m): *Roughly these values are divided by 5m To sum up with the analogue FE… Front-End construction Finished Amplifier characterization OK (minor modifications to do) Potential sensor location identified Cables availability guaranteed (but we’ve to take a look anyway) Cables length seems to be fine Signal amplitude estimated ( 50 – 100mV amplitude)

BE-BI-BL Jose Luis Sirvent Blasco Digital Front-End Status Test Set-Up: Emulating the system architecture Back-End System Front-End System Diamond Detector 3 x LHC Clock Tunnel Surface SMF 9/125um Message for the cleaning lady

Link States: 1. Start-up at Test-Mode : Known pattern to check synch. 2. Latency calculation : FE loops data 3. Link on Normal mode 4. Remote QIE10 Initialization 5. Trigger signal for data acquisition 6. Data capture : Stored on BE SDRAM memory 7. Stop Acquisition 8. Post-mortem data transmission SDRAM  PC BE-BI-BL Jose Luis Sirvent Blasco Digital Front-End Status Status of the TO-DO list for complete system operation BE-BI-BL Jose Luis Sirvent Blasco 15

BE-BI-BL Jose Luis Sirvent Blasco Digital Front-End Status First QIE10 acquisitions with function generator

BE-BI-BL Jose Luis Sirvent Blasco Digital Front-End Status Preparing synchronous acquisitions The idea: To use a system CLK 40Mhz for Igloo2 REFCLK and to trigger F.Generator Pulses on synch with 40MHz System CLK propagated to FE Latency/Phase deterministic system Synchronous acquisitions on FE The objective: Test jitter performance Check TDC functionality Check ADC linearity System CLK Synchronous Pulses (Charge) Back-End TX CLK Front-End RX CLK

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Write Operation BE-BI-BL Jose Luis Sirvent Blasco 20

Continuous Write Operation BE-BI-BL Jose Luis Sirvent Blasco 21

Console Application BE-BI-BL Jose Luis Sirvent Blasco 22

Counter TESTS (coreUART baud) BE-BI-BL Jose Luis Sirvent Blasco 23 1:18 min

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1. The BWS Readout Upgraded System 1.1 Architecture BE-BI-BL Jose Luis Sirvent Blasco 25 Usage of the GBT link for Data, Control and Timing transmission FE BE GBT 4.8Gbps Beam Synchronous measurements Two serious candidates as readout ASIC for pCVD diamond Detector: ICECAL (LHCb) QIE10 (CMS) We’ll design for tunnel radiation levels: 100Gy/year  up to 1KGy (10 years)

BE-BI-BL Jose Luis Sirvent Blasco The BWS Readout Upgraded System 1.2 Front-End Board (QIE10 Acquisiton) Igloo2 UMd Mezzanine Board Experiment CMS: T.Grassi & T. O’Banon Usage: GBT Link for ngCCM QIE10 Mezzanine Board Experiment BI BWS: J.L. Sirvent Usage: Digitalization pCVD Diamond Detector SMA VTRx Power Vcc = 6v SMF 9/125 Control/Debug System seen as a Black Box

BE-BI-BL Jose Luis Sirvent Blasco The BWS Readout Upgraded System 1.2 Front-End Board (Assembly tests)

2. Planning laboratory tests 2.1 Test schematic: BE-BI-BL Jose Luis Sirvent Blasco 28 Link States: 1. Start-up at Test-Mode : Known pattern to check synch. 2. Latency calculation : FE loops data 3. Link on Normal mode 4. Remote QIE10 Initialization 5. Trigger signal for data acquisition 6. Data capture : Stored on BE SDRAM memory 7. Stop Acquisition 8. Post-mortem data transmission SDRAM  PC

2. Planning laboratory tests 2.1 Test schematic: BE-BI-BL Jose Luis Sirvent Blasco 29 Link States: 1. Start-up at Test-Mode : Known pattern to check synch. 2. Latency calculation : FE loops data 3. Link on Normal mode 4. Remote QIE10 Initialization 5. Trigger signal for data acquisition 6. Data capture : Stored on BE SDRAM memory 7. Stop Acquisition 8. Post-mortem data transmission SDRAM  PC

2. Planning laboratory tests 2.1 Test schematic: BE-BI-BL Jose Luis Sirvent Blasco 30 Link States: 1. Start-up at Test-Mode : Known pattern to check synch. 2. Latency calculation : FE loops data 3. Link on Normal mode 4. Remote QIE10 Initialization 5. Trigger signal for data acquisition 6. Data capture : Stored on BE SDRAM memory 7. Stop Acquisition 8. Post-mortem data transmission SDRAM  PC High Speed lines Looped