1. Student Meeting Jose Luis Sirvent PhD. Student 27/01/2014
Beam Secondary Shower Acquisition System: System Planning and developments to do
Student Meeting
Jose Luis Sirvent
PhD. Student
27/01/2014

2. 1.An Schematic of the desired final system with GBTx Initial Board with QIE10
Power Supply
12V
DC/DC 5V
DC/DC
3.3V
DC/DC
1.5V
DC/DC
2.5V
CMOS (3.3V)
CLK
40Mhz
CImode
Switch
Switches
Switches
QIE10 A
SRin
Mode
[0:3]
I2C Address
[0:3]
MAX9179
SRck
Out [0:7]
80Mhz
SRload
GBTx
Reset
80Mhz
Connector
I2C
SRreset
I2C
[0:3]
MAX9376
SRread
QIE10
SC-Read LVDS [0:1]
SRout
MAX9179
MAX9112
SRout
CLK
40Mhz
SRreset
QIE10 B
SRread
2.5V
(VccRx=VccTx)
Out [0:7]
80Mhz
I2C Rd Td
CImode
SRin
VTRx
MAX9179
SRck
Reset
80Mhz
SRload
MAX9376
QIE10
SC-Write SLVS [0:9]

3. 1.An Schematic of the desired final system with GBTx Front-End & Back-End architecture (Different options for FE module)
TTC
GBTx ASIC
Not available up to now!
In Q we’ll have some
Needed to implement GBT protocol
Arria V
Igloo2
SFP+
NEW VFC
VME FMC Carrier Board
BOBR
VME Board
Ethernet
SFP+
FMC Connector
FPGA
Arria V
Clk_bunch
Clk_Turn
Clk_Events
Back plane VME64 Connector
Back plane VME64 Connector
SFP+
SFP+
Memory
Memory
SFP+
SFP+
Front-End #2
Front-End #1
AD41240
Versatile Link
VTTr
-6dB
Versatile Link
VTTr
+34dB
Data
QIE10 A AD
12Bits
Filter
Shaper
-26dB
Control
-12dB
QIE10 B AD
12Bits
Filter
Shaper
GBTx&GBT-SCA Or
Igloo2 FPGA
GBTx&GBT-SCA Or
Igloo2 FPGA
Data
Selection Logic DC
-32dB AD
12Bits AD
12Bits
Filter
Shaper
CLK
CLK DC AD
12Bits

4. Conversion Module modified for VTRx
1. Initial Developments with Igloo GBT protocol implementation and testing in Igloo2
Fibre Optic
TTC, Data, Control
Monitoring PC
Hitech Global
SMA To SFP/SFP+
Conversion Module modified for VTRx
Igloo2 Development board with
GBTx firmware emulation
Motivation:
The outcome of this tests would be to verify the usability of Igloo2 as GBT driver on Front-Ends.
The system should be designed in a way that the same Igloo2 emulates two separated systems.
Tasks:
1. Contact Hitech Global to verify module availability, compatibility and possible modification for VTRx’s
2. Contact Tullio Grassi & others to find GBT firmware for Igloo2, otherwise development in Igloo2 needed based on other FPGA’s from GBT-FPGA.
3. Once Implemented ,the GBT link should be evaluated in terms of BER, Timing and synchronization, Eye diagram…

5. But relatively simple layout Conversion Module modified for VTRx
1. Initial Developments with Igloo GBT protocol implementation and testing in Igloo2
Not so nice…
Price  ~ 490$
But relatively simple layout
Do it ourselves?
Original Price  399$
Price for us  99 $ !!
We save 300$ !!
Fibre Optic
TTC, Data, Control
Monitoring PC
Hitech Global
SMA To SFP/SFP+
Conversion Module modified for VTRx
Igloo2 Development board with
GBTx firmware emulation
Motivation:
The outcome of this tests would be to verify the usability of Igloo2 as GBT driver on Front-Ends.
The system should be designed in a way that the same Igloo2 emulates two separated systems.
Tasks:
1. Contact Hitech Global to verify module availability, compatibility and possible modification for VTRx’s
2. Contact Tullio Grassi & others to find GBT firmware for Igloo2, otherwise development in Igloo2 needed based on other FPGA’s from GBT-FPGA.
3. Once Implemented ,the GBT link should be evaluated in terms of BER, Timing and synchronization, Eye diagram…

6. Conversion Module modified for VTRx
1. Initial Developments with Igloo GBT protocol implementation in Back-End module and initial communication testing
Monitoring PC
Fibre Optic
TTC, Data, Control
VFC Board Or
Arria V Dev. Kit
Monitoring PC
Back-End module
Hitech Global
SMA To SFP/SFP+
Conversion Module modified for VTRx
Igloo2 Development board with
GBTx firmware emulation
Motivation:
The aim of this test would be to finish with the interface Front-End <-> Back-End, issues such as the synchronization of the front-end with the LHC clock is to be addressed.
Tasks:
1. The Back-End board has to be available or at least a development board to simulate the VFC board.
2. We’ll need some support/development in the Back-end side to implement the GBT protocol in an Arria V or VFC board
3. The communicacion will be tested with long links ~200m and the synchronization of both sides will be studied as well as BER. At the end of this task the GBT protocol in both sides has to be completelly implemented, tested & guaranteed.

7. 1. Initial Developments with Igloo2 1
1. Initial Developments with Igloo Interface the QIE10 Asics with the FPGA
Power
Pulse Generator
QIE10 A
SMA
Connector
Pulse Generator
QIE10 B
SMA
Laboratory Equipment
Monitoring PC
QIE10 Test Board
Needed to be developed
Igloo2 Development board with
GBTx firmware emulation
Motivation:
The outcome of this task is the development of a QIE10 board to interface with the FPGA, the QIE10 control, initialization sequence and synchronization will be embedded on the FPGA code.
Tasks:
1. We have to get some QIE10 for our tests (Availability??)
2. Again it will be necessary to get some information from Tulio or other experiments regarding the QIE10 & Igloo2 connectivity & firmware, otherwise VHDL development will be necessary.
3. The development of a QIE10 board is mandatory in order to test the interface (schematics should be provided and a board has to be fabricated). So far, there are no existing QIE10 dev boards.
4. Once fabricated the boards, each chanel has to be calibrated (a calibration table is needed to compensate QIE10 imperfections)

8. 1. Initial Developments with Igloo2 1
1. Initial Developments with Igloo pCVD, splitting system & QIE10 digitalization
Power
Passive
Splitting System
Coax Cable
50 ohm
(1-10m)
QIE10 A
SMA
pCVD
Connector
QIE10 B
Cividec
Module
SMA
RF Resistive network
Monitoring PC
QIE10 Test Board
Needed to be developed
Igloo2 Development board with
GBTx firmware emulation
Motivation:
The outcome of these tests would be to test the that splitting chain of the pCVD performs well (mainly based on RF components and a resistive network) and that the QIE10 digitalization is well controled and interfaced with the Igloo2 FPGA. The noise levels or pedestrials are to be measured and the front-end scheme validated for final use on the tunnels.
Tasks:
1. We have to buy/get a pCVD module from Cividec for system testing and noise measurements on the very front-end (splitting system)
2. Initial testing would be done with a radiation source on the pCVD side and interfaced with the QIE10 board for system
3. For possible tests without radiation source the pcvd could be substituted by a pulse generator (less realistic results)

9. 1. Initial Developments with Igloo2 1
1. Initial Developments with Igloo Complete test assembly for Proof of concept evaluation
QIE10 A
Power
Connector B
SMA
Coax Cable
50 ohm
(1-10m)
QIE10 Test Board
Needed to be developed
Passive
Splitting System
Monitoring PC
pCVD
Cividec
Module
VFC Board Or
Arria V Dev. Kit
RF Resistive network
Igloo2 Development board with
GBTx firmware emulation
Motivation:
The final proof-of-concept can be evaluated by using this assembly. The Igloo2 in this case could be configured to act purely as a GBTx asic, this way the system could be suitable to work with Igloo2 or GBTx in case of change for final board.
Tasks:
The system has to be configured to work in a complete assembly by using the knowledge from the previous tasks.
The set-up should be done in a way to make possible Igloo2-> GBTx migration.
Final tests and evaluation has to be done in with the assembly for system demonstration
At this point a decision could be done regarding the FPGA usage or the development of a compact board with GBTx.

10. Compact Front-End Board VME FMC Carrier Board (VFC)
1. Initial Developments with Igloo Development of a compact board for BWS pCVD diamond detector readout
TTC
SFP+
NEW VFC
VME FMC Carrier Board
BOBR
VME Board
Ethernet
SFP+
FMC Connector
FPGA
Arria V
Clk_bunch
Clk_Turn
Clk_Events
Power
Back plane VME64 Connector
Back plane VME64 Connector
VTRx
SFP+
Passive
Splitting System
QIE10 A
SMA
Fibre Optic
TTC
Data
Control
SFP+
pCVD
Igloo2 Or
GBTx
Memory
Memory
SFP+
QIE10 B
SMA
Cividec
Module
SFP+
RF Resistive network
Compact Front-End Board
Needed to be developed
VME FMC Carrier Board (VFC)
Back-End VME Crate
Motivation:
Finally the last part of the project would be the development and testing of a very simple and compact board containing the Rad-Hard or Rad-Tol components.
Tasks:
The QIE10 development board previously done has to be extended house the FPGA (or GBTx) and VTRx in the same board.
Extensive testing has to be done in this board to guarantee that the performance reached in the development kits is repeated in this version.
Radiation studies are also important to characterize the complete radiation hardness of the board and identify failures.
This system could be installed in paralel with an operational BWS PMT & Scintillator system to crossvalidate performances.

11. 2. Alternatives to QIE10, plan B? High Dynamic range but not so nice…
FE-Readout
Technology
Cum_Dose
Din_Range
Integ_ADC Fs
Contact
Info
QIE10
350nm SiGe
400Gy -3KGy
3.1fC-320pC
1e5
Yes / 8bits
40Mhz
J.Mans (CMS)
Link
EasiRoc
160fC-320pC
2e3 No
---
S.Callier (Omega)
Fatalic3
IBM 130nm
24fC-1000pC
4e4
N.Pillet (LCF)
PACIFIC
750fC-30pC 40
Yes / 6bits
IBMS ASIC
300Gy
1e3
ICECAL2
SiGe BiCMOS 0.35um
4e3
E. Picatoste (UB)