1. Beam Secondary Shower Acquisition System: RF design techniques for 40MHz ADC Student Meeting Jose Luis Sirvent PhD. Student 30/09/2013

2. Previously on Jose’s PhD… 4. How is the system now? (DC-156MHz) PMT Amplifier Active Low Pass Filter CK50 Coax 250m IBMS Acquisition Board Active Low-Pass G=20 Fc=159MHz EDA-01716 Nominal LHC 25nsRF 5ns

3. Previously on Jose’s PhD… 4. How is the system now? (DC-156MHz) PMT Amplifier Active Low Pass Filter CK50 Coax 250m IBMS Acquisition Board Nominal LHC 25nsRF 5ns 1st 40Mhz 2nd 80Mhz 1st 120Mhz 3rd 160Mhz 1st 200Mhz 2nd 240Mhz Noise 2nd 400Mhz 1st 600Mhz

4. Previously on Jose’s PhD… 4. How is the system now? (DC-156MHz) PMT Amplifier Active Low Pass Filter CK50 Coax 250m IBMS Acquisition Board Nominal LHC 25nsRF 5ns 1st 40Mhz 2nd 80Mhz 1st 120Mhz 3rd 160Mhz 1st 200Mhz 2nd 240Mhz Noise 2nd 400Mhz 1st 600Mhz What I see here?: 1.There is a bit of Bunch overlap (cable) + 2.Filter removes high freq noise + 3.Integrator performs also high freq cleaning + 4.No immunity to low freq noise <4Mhz (Affecting the whole scan quality) - 5.Base-line Variations could cause detection of more or less charge per bunch – Detector leakage current (adjustments needed), lines noise…

5. Previously on Jose’s PhD… 4. How could be the simplest improvement? pCVD RF Amplifier 140MHz-160MHz CK50 Coax 250m VFC ADC Mezanine Board Band-Pass 140MHz-160MHz RF 5ns Nominal LHC 25ns 1st 40Mhz 2nd 80Mhz 1st 120Mhz 3rd 160Mhz 1st 200Mhz 2nd 240Mhz Noise 2nd 400Mhz 1st 600Mhz

6. Previously on Jose’s PhD… 4. How could be the simplest improvement? pCVD RF Amplifier 140MHz-160MHz CK50 Coax 250m VFC ADC Mezanine Board Band-Pass 140MHz-160MHz RF 5ns Nominal LHC 25ns 1st 40Mhz 2nd 80Mhz 1st 120Mhz 3rd 160Mhz 1st 200Mhz 2nd 240Mhz Noise 2nd 400Mhz 1st 600Mhz What are the advantages?: 1.Reduction of BW is also a reduction of the noise + 2.High Freq noise inmunity and Low Freq noise inmunity increased + 3.Bunch overlap reduced and less dependency of cable length+ 4.The possible detector leakage is not (or not so) important + 5.Mean power dissipated by FE components and lines = 0 w + 6.Possibility of face the problem with RF design techniques (+ - ?) 7.We cannot perform integration (mean bunch charge =0c) - 8.Depending frequency planning, needed ADC’s 80,120,200MSPS (+ - ?)

7. Previously on Jose’s PhD… 4. How could be the simplest improvement? pCVD RF Amplifier 140MHz-160MHz CK50 Coax 250m VFC ADC Mezanine Board Band-Pass 140MHz-160MHz RF 5ns Nominal LHC 25ns 1st 40Mhz 2nd 80Mhz 1st 120Mhz 3rd 160Mhz 1st 200Mhz 2nd 240Mhz Noise 2nd 400Mhz 1st 600Mhz What are the advantages?: 1.Reduction of BW is also a reduction of the noise + 2.High Freq noise inmunity and Low Freq noise inmunity increased + 3.Bunch overlap reduced and less dependency of cable length+ 4.The possible detector leakage is not (or not so) important + 5.Mean power dissipated by FE components and lines = 0 w + 6.Possibility of face the problem with RF design techniques (+ - ?) 7.We cannot perform integration (mean bunch charge =0c) - 8.Depending frequency planning needed ADC’s 80,120,200MSPS (+ - ?)

8. 5.And now, how to digitalize this? pCVD RF Amplifier 140MHz-160MHz CK50 Coax 250m VFC ADC Mezanine Board Band-Pass 140MHz-160MHz Nominal LHC 25ns

9. 5.And now, how to digitalize this? pCVD RF Amplifier 140MHz-160MHz CK50 Coax 250m VFC ADC Mezanine Board Band-Pass 140MHz-160MHz Nominal LHC 25ns A)At 40MSPS: Under-sampling technique We’ll have one sample per bunch + Good synchronization with other BWS systems + The SNR of the digital signal is depends of ADC jitter + External clk jitter - Availability of 12 bits ADC @ 40MSPS and BW > 150MHz + Jitter Impact

10. 5.And now, how to digitalize this? pCVD RF Amplifier 140MHz-160MHz CK50 Coax 250m VFC ADC Mezanine Board Band-Pass 140MHz-160MHz Nominal LHC 25ns B) At 320MSPS: Ideal ADC operation (Nyquist BW <= Fs/2) + We’ll have 8 samples per bunch (+ Reconstruction) (- Amount of data) Synchronization with other systems? (Optical position sensor) + -? Availability of 12 bits ADC @ 370MSPS + - ?

11. 5.And now, how to digitalize this? pCVD RF Amplifier 140MHz-160MHz CK50 Coax 250m VFC ADC Mezanine Board Band-Pass 140MHz-160MHz C) What we would like to have? A sample per bunch (40MSPS) For this we’d need or (A) or slow down the signal by RF design to 20Mhz to fit Nyquist Move one of the higher harmonics (120-240Mhz) to Base-Band (20Mhz) Slow signals are easier to process, and it’s electronics cheaper to build We’d be able to work up to 16bits ADC’s, no need of integrator. Many BPM systems work like this (See references) *D. Teytelman. Optimization of Bunch-to-Bunch Isolation in instability feedback systems. IBIC2013 Oxford *Y.B. Yan, et al. Beam Diagnostics System for a Photo-Neutron Source driven by 15MeV Electron Linac. IBIC2013 Oxford *A. Guirao, et al. Development of th enew electronic instrumentation for the Lipac/IFMIF beam position monitors. IBIC2013 Oxford *J.L. Gonzalez et al. Development of a High Dynamic Range Beam position Measurement system using Logaritmic amplifiers for the SPS at CERN. IBIC2013 Oxford …. And many others… LO

12. 5.And now, how to digitalize this? C)What we would like to have? 250m Cable pCVD 240Mhz30Mhz 220Mhz

13. 5.And now, how to digitalize this? C)What we would like to have? 250m Cable pCVD 240Mhz30Mhz 220Mhz

14. 5.And now, how to digitalize this? C)What we would like to have? 250m Cable pCVD 240Mhz 30Mhz 220Mhz

15. 5.And now, how to digitalize this? C)What we would like to have? 250m Cable pCVD 240Mhz 240Mhz-220Mhz 20Mhz 240Mhz30Mhz 220Mhz

16. 5.And now, how to digitalize this? C)What we would like to have? 250m Cable pCVD 240Mhz30Mhz 220Mhz

17. 5.And now, how to digitalize this? C)What we would like to have? 250m Cable pCVD 240Mhz30Mhz 220Mhz 20Mhz

18. 5.And now, how to digitalize this? C)What we would like to have? 250m Cable pCVD 240Mhz30Mhz 220Mhz System Validation 25ns: Let’s see settling time (Train of identical bunches)

19. 5.And now, how to digitalize this? C)What we would like to have? 250m Cable pCVD 240Mhz30Mhz 220Mhz System Validation 50ns: Let’s see settling time (Train of identical bunches)

20. 5.And now, how to digitalize this? C)What we would like to have? 250m Cable pCVD 240Mhz30Mhz 220Mhz System Validation 75ns: Let’s see settling time (Train of identical bunches)

21. 5.And now, how to digitalize this? C)What we would like to have? 250m Cable pCVD 240Mhz30Mhz 220Mhz System Validation 5ns: Let’s see settling time (Train of identical bunches)

22. 5.And now, how to digitalize this? C)What we would like to have? Other way to validate the new proposal: Loading effect on cable (Bunch isolation) Point APoint B Point APoint B Point A Transient Ringing Pile-Up Conclusions: In terms of Settling time the use of band-pass filters guarantees a quicker response (+) With this approach the bunch overlap effect has been reduced (+) The main frequency of the acquisition system has been moved to 20MHz (+) The system is ‘independent’ of cable length, only seen as loses, not as dispersion (+) This system could be used at 40MSPS, complying with the Nyquist criteria BW <= Fs/2 (+) With this previous system, we can use a commercial and cheap ADC FMC mezanine board in the VFC (+) The system behaviour is like an integrator with Tintegration=12.5ns & Tdischarge=12.5ns (+) Needed to develop a good quality 2 nd order RF filters and amplifiers. Since 2 cables reach the back-end, the system should be replicated twice (-) Needed to provide clean and tuned tone of 220Mhz for mixer (-)

23. 6.Front-End Development Status: Material Available: – SMA Adapters & Cables – SMA -6dB Power splitters – SMA Attenuators (10, 20 & 30dB) – Cividec amplifiers Material needed: – Cividec pCVD diamond detector – Amplif. Mini-circuits Gali-52 eval board ? – Radiation source for MIP tests (Timing & Spectra) Actions required: – Better understanding accelerators timing – Define some tests procedures in SPS BWS to be prepared for beam. – Continue reading IBIC2013 contributions for more ‘inspiration’ – Finish the “Options proposal” stage and start the “Decision making” stage. – Training : VHDL (foreseen for 14-18 Oct. 2013 but I’ll use next two weeks to prepare the course) – Training : CAS (foreseen for 4-8 Nov. 2013) – Training : ISOTDAC (foreseen for 28 Jan. – 5 Feb. 2014) ? 5 th International School of Trigger and Acquisition Electronics (Budapest, Hungary) Web: http://isotdaq2014.wigner.mta.huhttp://isotdaq2014.wigner.mta.hu Programme: http://indico.cern.ch/conferenceOtherViews.py?view=standard&confId=209985http://indico.cern.ch/conferenceOtherViews.py?view=standard&confId=209985 Poster: http://isotdaq2014.wigner.mta.hu/pics/isotdaq2014_poster.pdfhttp://isotdaq2014.wigner.mta.hu/pics/isotdaq2014_poster.pdf Video: http://cds.cern.ch/record/1342126http://cds.cern.ch/record/1342126

26. 50ns

27. 25ns

28. 5ns