1. Student Meeting Jose Luis Sirvent PhD. Student 12/08/2013
Beam Secondary Shower Acquisition System: Dynamic range coverage and initial designs
Student Meeting
Jose Luis Sirvent
PhD. Student
12/08/2013

2. 1. Previously on Jose’s PhD…
4 Studies carried out for the moment (With 3 reports available):
pCVD Signal estimations from Wire Scanners
Dynamic range first approximations for SPS
SPS max Charge per bunch (All BWS)_Totem: 120pC
SPS max Charge per bucnh (Prototype Location 51740)_Nominal: 60pC
Dynamic range first approximations for LHC
LHC max Charge per bunch E=2e-6m 7TeV (Beam_Sigma=181um)_Nominal: 226pC
LHC max Charge per bunch E=2e-6m 450GeV (Beam_Sigma=716um)_Nominal: 32pC
Proposal of Dynamic range: 2fC (~MIP) to 400pC (~2*Qmax)
Impact of Long Cables (250m of CK50) in the pCVD Signal (Report)
250m Cable Bandwidth: ~ 10MHz (To avoid 25ns pulse overlapping needed > 40MHz)
Amplitude loss of 5dB
Observed offset due pulse overlapping 5%
Settling time ~ 66ns (first 3 bunches)
BWS Scan Simulation Though Long CK50 Cables (Report)
pCVD Signal generation from BWS and Beam characteristics (Script)
Matlab processing and simulation of cable as an approximate filter (Script)
Sigma measurement not affected by cable
Very low temporal resolution at bunch level (too long decays)
Not constant offset. This is good, bad…?
CK50 Cable Measurements in the SPS for BWS Prototype location (Report) New!
Pspice Model and analytical expressions validated!
Extraction of a reliable Matlab model for CK50 and other coaxial cables, also validated with real data.
Noise study of 176m of CK50, frequency, temporal and amplitude distribution.
Pulse distortion study

3. 2. Going back to the pCVD din. range calculations…
pCVD Signal estimations from Wire Scanners
Dynamic range first approximations for SPS
SPS max Charge per bunch (All BWS)_Totem: 120pC ( ~7.5e4 MIP)
SPS max Charge per bucnh (Prototype Location 51740)_Nominal: 60pC ( ~3.7e4 MIP)
Dynamic range first approximations for LHC
LHC max Charge per bunch E=2e-6m 7TeV (Beam_Sigma=181um)_Nominal: 226pC (1.5e5 MIP)
LHC max Charge per bunch E=2e-6m 450GeV (Beam_Sigma=716um)_Nominal: 32pC (2e4 MIP)
1st Proposal of Dynamic range: 1.6fC (~MIP) to 400pC (2.5e5 MIPS)
(Study from Accelerator Specs and Existing BWS locacions)
We can also simplify estimations by using some “User-Based experience” (Thanks Ana!):
PSB:
“The min in PSB is ~1mm, the max, I do not know for sure but up to now I've found ~7mm”: Sigma 1-7mm
PS:
“The smallest sizes measured are in the order of 1mm too. But the largest I think is around 12mm! (TOF inj) ”: Sigma 1-12mm
SPS:
“ I don't think there is a measurement under 0.2mm”: Sigma 0.2-4mm
LJHC:
“Current sizes should  be a good estimation: Sigma 0.1 – 1.5mm
B1 -> By=287.81m, Bx=165.48m, Dy=0.1032, Dx= m B2 -> By=404.55m, Bx=123.51m, Dy= , Dx=0.1168m

4. A) PSB (1-7mm) C)SPS (0.2-4mm)
B) PS (0.6-12mm)
D) LHC ( mm)

5. 2. Going back to the pCVD din. range calculations…
Therefore new possible specs:
Detector at 2m
Sigma range: um
Energy range: 450 – 7000MeV;
Bunch Intensity range: 0.055e11 – 1.1e11
New proposal for Din.Range: 1 – 1e6 MIPs (1.6fC – 1600pC)

6. 3. How to cover such dynamic range: 3. 1 Edwald had a nice idea
3. How to cover such dynamic range: 3.1 Edwald had a nice idea! 3x12Bits ADC’s
Characteristics:
3 Lines (34,-12&-52dB)
Min voltage to digitalize in each line: 2mV
Good SNR in the whole range
Quantification error < <1% in the whole range
More bits  Less error 
Possible Drawbacks:
Needed good timing (low jitter) for T.Bunch
Maybe needed shaper before ADC’s
Keep signal while digitalization
Maybe needed high sampling speed to ‘Capture well all the bunches’

7. 3. How to cover such dynamic range: 3
3. How to cover such dynamic range: 3.2 QIE10 inspired (If long lines used!)
Characteristics:
3 Lines (34,-12&-52dB)
Min voltage to digitalize in each line: 2mV
Good SNR in the whole range
Quantification error % in the whole range
Only 24 Bits needed
Jitter not-so important
Shaper not needed
Possible Drawbacks:
Quantification error!
Not standard solution
Never used the whole range of one QIE10
Line A: Amp. Saturation

8. 3. How to cover such dynamic range: 3
3. How to cover such dynamic range: 3.3 QIE10 inspired (Digitalization on tunnel)
Characteristics:
2 Lines (14 & -26dB)
Min voltage to digitalize in each line: 0.2mV
Shorter cables ~ less noise?
Quantification error % in the whole range
Only 16 Bits needed
Possible Drawbacks:
Not standard solution
Never used the whole range of one QIE10
Line A: Amp. Saturation at 1V
Tunnel Front-End development
Maybe possible to use CMS QIE boards?
Development justification:
Pros:
Smart solution with an optical data link
Charge always provides more info than peak detection.
Would be a last-generation detector system:
Many of the needed components are cutting-Edge.
Radical Architectural change respect to current BWS systems.
No pile-up effect for bunch by bunch
Cons:
Not yet clear…
The cable length is maybe not so critical
The cable noise could be compensated by filtering/Amplification.
Standard ADC’s provide good quantification error and could cover all the dynamic range.
Maybe other possibilities available for charge integration.

9. Successors : OMEGA/Orsay « ROC chips »
Move to Silicon Germanium 0.35 µm BiCMOS technology in 2004
Readout for MaPMT and SiPM for ILC calorimeters and other applications
Very high level of integration : System on Chip (SoC)
MAROC3
HARDROC2
MICROROC1
Chip
detector ch
DR (C)
MAROC
PMT 64
2f-50p
SPIROC
SiPM 36
10f-200p
SKIROC Si
0.3f-10p
HARDROC
RPC
2f-10p
PARISROC PM 16
5f-50p
SPACIROC
5f-15p
MICROROC
µMegas
0.2f-0.5p
SKIROC2
SPIROC2
SPACIROC
PARISROC2
25ns Integration??
15 jun 2012
CdLT Photodet conference

10. 4. Some questions that need answer for design.
Which temporal resolution we need? (1ns – 25ns)
Which sampling frequency we want? (40MHZ -1GHz)
40Mhz (Integration or peak detection?) – 1GHz (More information and possible post-processing)
What we want to measure, charge (Qie10) or voltage values (ADC’s)?
Maybe possible to use other chips for integration (Gated integrators like the one used now)
Do we have buffer size limitations? (Scan time 1m/s > 300ms  450KBytes)
High sampling freq  Lot of information per scan

11. 5) Front-End Detector Proposals: A) BLM Style (Quick assembly): Ewald’s schemeHV
Cividec
Amplifier
34dB
Cividec
AC-DC Splitter
-6dB
Cividec
Diamond Detector
Mini-Circuits
DC-4GHz
Splitter AC
40dB
pCVD
-6dB
12V DC
Tunnel DC
-6dB
-12dB
-6dB
Mini-Circuits
DC-4GHz
Splitter
-52dB
Cividec
Attenuator
-6dB
-40dB
Surface

12. MicroStript Front-End
5) Front-End Detector Proposals: B) Microstript development (Integrated solution)
12V HV
MicroStript Front-End
Board Development 1
34dB
Cividec
Diamond Detector
pCVD
Tunnel DC
-6dB
MicroStript Back-End
Board Development 2
-12dB
-6dB
-52dB
Surface

13. MicroStript Front-End
5) Front-End Detector Proposals: C) Full-Custom Design (Integrated solution) HV
12V
34dB
pCVD
MicroStript Front-End
Board Development 1
Tunnel DC
-6dB
MicroStript Back-End
Board Development 2
-12dB
-6dB
-52dB
Surface

14. 6) Development of a GUI Reasons:
Complete Wire Scan simulation from Beam, cable, amplification and acquisition properties.
Evaluation of Digitalization Schemes (ADC VS QIE)
Study of impact of the long cable in sigma determination.
Extraction of BbB profiles. Quantification of error.
Study of coverage of Din.Range with different lines.
Include noise sources (not yet done)

15. 6) Development of a GUI A. User interface

16. 6) Development of a GUI B. Bunch Information
Calculations of beam sigma from beam parametres
Aspect ratio Beam/wire
Number of interacting particles per bunch
Charge generated in the pCVD detector

17. 6) Development of a GUI C. Cable Impact
II. Complete scan before and after cable (Raw)
I. Transfer Function
Voltage signal from charge in detector with adapted lines (50ohm)
Two possible cables in study CK50& LDF5
Evaluation of loses and pulse dispersion
Evaluation of signal offset during scan
Design of a suitable shaper in case of needed (Recover baseline)
III. Study of the Shaper response

18. 6) Development of a GUI D. Amplification in lines
Voltage values in each line during scan
Study of saturation points of amplifiers
Initial estimations for SNR for each line

19. 6) Development of a GUI D. Digitalized values of lines (ADC & QIE)
I. Digitalized values with ADC’s
II. Digitalized values with QIE10 + Quantif Errors
One sample per bunch in this case
ADC Fs= 40MHz
QIE10 Int=25ns
Study of the Gauss fit Sigma to check errors due ADC/QIE + Cable
Study of saturation of ADC’s & QIE10
Clear view of digitalized profile with QIE and it’s different resolutions
Impact of Tbunch Jitter in both digitalization schemes (not jet included)

20. 6) Development of a GUI D. Digitalized values of lines (Detail QIE)

21. 6) Development of a GUI E. 1 Bunch Profile in lines (ADC & QIE)
I. 1Bunch profile with ADC’s
II. 1Bunch profile with QIE10’
Study of accuracy of digitalization schemes and errors of fitting (Sigma)
Independent study per line
Combine the different lines and study the fitting errors (not yet done)
Study quantification error of combined lines (not yet done)

22. 6) Development of a GUI F. Bunch Peak detection VS Bunch Integration
I. Bunches peak detection Before/After cable & Ratio
II. Bunches charge values Before/After cable & Ratio
Another way to see the Cable effect
Another way to compare Peak detection (ADC) VS Integration (QIE)
Without shaper the baseline increments very slowly (0.0004% ADC & 0.007% QIE10)
No significant effect in Sigma of the whole scan
“Same” charge value before and after cable (1% loss due to cable)
Shaper doesn’t seems to help too much for ADC (needed more studies)
II. Bunches peak detection Before/After cable & Ratio with Shaper

23. GUI Validation: SPS.BWS.41677.V
0.3% error
0.1% error

24. GUI Validation: SPS. BWS. 41677
GUI Validation: SPS.BWS V Digitalization error comparison ADCs VS QIEs

25. GUI Validation: SPS.BWS.41677.V 50ns Spacing 20MHz ADC

26. GUI Validation: SPS.BWS.41677.V 50ns Spacing 50ns int QIE