1 ACTAR meeting – Santiago March 2008 Requirements Features required not available in standard ASICs for HEP: Auto-triggerable. Large dynamic range. Low.

Slides:



Advertisements
Similar presentations
The Industry’s Smallest 16 Bit ADC’s
Advertisements

SPI Serial Peripheral Interface. SPI Serial Peripheral Interface is communication between two devices, one bit at a time sequential one bit at time over.
JRA01: ACTAR Collaboration : GANIL, DAPNIA Saclay, CENBG Bordeaux, Univ. Liverpool, Daresbury, GSI, Univ. Santiago de Compostela Objectives: Investigate.
Specific requirements for analog electronics of a high counting rate TRD Vasile Catanescu NIHAM - Bucharest CBM 10th Collaboration Meeting Sept 25 – 28,
Data Acquisition Systems ACES Presentation Brad Ellison March 11, 2003.
Front-end electronics for Time Projection Chamber I.Konorov Outlook:  TPC requirements  TPC readout options  Options for TPC FE chips  Prototype TPC.
HEP2005, Lisboa July 05 Roberto Campagnolo - CERN 1 HEP2005 International Europhysics Conference on High Energy Physics ( Lisboa-Portugal,
ACTAR Nov 05 Lolly Pollacco CEA Saclay Front End Electronics for ACTAR.
28 August 2002Paul Dauncey1 Readout electronics for the CALICE ECAL and tile HCAL Paul Dauncey Imperial College, University of London, UK For the CALICE-UK.
Large Area, High Speed Photo-detectors Readout Jean-Francois Genat + On behalf and with the help of Herve Grabas +, Samuel Meehan +, Eric Oberla +, Fukun.
DP Cabinet.
PH4705/ET4305: A/D: Analogue to Digital Conversion Typical Devices: Data sheets are on the web site for A/D 8 bit parallel AD7819 and serial ADC0831 And.
© The McGraw-Hill Companies, Inc McGraw-Hill 1 PRINCIPLES AND APPLICATIONS OF ELECTRICAL ENGINEERING THIRD EDITION G I O R G I O R I Z Z O N I 15.
ECE 477 DESIGN REVIEW TEAM 2  FALL 2011 Members: Bo Yuan, Yimin Xiao, Yang Yang, Jintao Zhang.
Technical Training. 1 Configuration: 2558 Analog Input Module 1. Select voltage or current input mode for each channel 3. Select digital filtering, offset.
P. Baron CEA IRFU/SEDI/LDEFACTAR WORKSHOP Bordeaux (CENBG) June 17, Functionality of AFTER+ chip applications & requirements At this time, AFTER+
1 E. Delagnes Saclay Dec 3rd CLAS12 Micromegas Tracker: FE electronics
September 8-14, th Workshop on Electronics for LHC1 Channel Control ASIC for the CMS Hadron Calorimeter Front End Readout Module Ray Yarema, Alan.
S.Vereschagin, Yu.Zanevsky, F.Levchanovskiy S.Chernenko, G.Cheremukhina, S.Zaporozhets, A.Averyanov R&D FOR TPC MPD/NICA READOUT ELECTRONICS Varna, 2013.
P. Baron CEA IRFU/SEDI/LDEFACTAR Meeting Santiago de Compostela March 11, A review of AFTER+ chip Its expected requirements At this time, AFTER+
1 April 29, 1999 ZENO DATALOGGER Texas Natural Resource Conservation Commission.
ATtiny23131 A SEMINAR ON AVR MICROCONTROLLER ATtiny2313.
HINP32C Southern Illinois University Edwardsville VLSI Design Research Laboratory Washington University in Saint Louis Nuclear Reactions Group.
Alexei SemenovGeneric Digitizer Generic Digitizer 10MHZ 16 bit 6U VME Board.
NUMI Off Axis NUMI Off Axis Workshop Workshop Argonne Meeting Electronics for RPCs Gary Drake, Charlie Nelson Apr. 25, 2003 p. 1.
Acquisition Crate Design BI Technical Board 26 August 2011 Beam Loss Monitoring Section William Vigano’ 26 August
1 Luciano Musa, Gerd Trampitsch A General Purpose Charge Readout Chip for TPC Applications Munich, 19 October 2006 Luciano Musa Gerd Trampitsch.
Present Uses of the Fermilab Digital Signal Receiver VXI Module Brian Chase,Paul Joireman, Philip Varghese RF Embedded Systems (LLRF) Group.
BTeV Hybrid Pixels David Christian Fermilab July 10, 2006.
© 2009, Renesas Technology America, Inc., All Rights Reserved 1 Course Introduction  Purpose:  This course provides an overview of the serial communication.
Verification work Arild Velure. Goals As only part of the final functionality has been implemented for this MPW1, the focus for the testing has.
Team 2 Yimin Xiao Jintao Zhang Bo Yuan Yang.  An ability to sample analog voltage signal range from -12 V to 12 V via BNC;  An ability to reconstruct.
09/02/20121 Delay Chip Prototype & Delay Chip Test Board Joan Mauricio – Xavier Ondoño La Salle (URL) 12/04/2013.
1 Characterization of the PCA16 CERN, 14 th July 2008 M. Mager, L. Musa.
LC Power Distribution & Pulsing Workshop, May 2011 Super-ALTRO Demonstrator Test Results LC Power Distribution & Pulsing Workshop, May nd November.
ILD/ECAL MEETING 2014, 東京大学, JAPAN
Click to edit Master subtitle style Presented By Mythreyi Nethi HINP16C.
1 19 th January 2009 M. Mager - L. Musa Charge Readout Chip Development & System Level Considerations.
2/June/2009LHCb Upgrade1 Single ended ADC Differential ADC –Convert single ended signal to differential (use AD8138 amp) –ASIC differential output ADC.
ASIC Development for Vertex Detector ’07 6/14 Y. Takubo (Tohoku university)
Current Status of RICH LVL-1 Trigger Module Takashi Matsumoto and Ken Oyama Presentation Outline Topics Geometry of Trigger Tile Required function of RICH.
0808/0809 ADC. Block Diagram ADC ADC0808/ADC Bit μP Compatible A/D Converters with 8-Channel Multiplexer The 8-bit A/D converter uses successive.
Product Overview 박 유 진박 유 진.  Nordic Semiconductor ASA(Norway 1983)  Ultra Low Power Wireless Communication System Solution  Short Range Radio Communication(20.
ECE 101 Exploring Electrical Engineering Chapter 7 Data Acquisition Herbert G. Mayer, PSU Status 11/30/2015 Derived with permission from PSU Prof. Phillip.
Readout controller Block Diagram S. Hansen - CD-1 Lehman Review1 VXO Ø Det Links to 24 SiPM Front End Boards Clock Event Data USB ARM uC A D Rd Wrt 100Mbit.
1 E. Delagnes Saclay Dec 3rd FE electronics for Micromégas Trackers
CEA DSM Irfu IDeF-X HD Imaging Detector Front-end for X-ray with High Dynamic range Alicja Michalowska, CEA-IRFU 1 Journées VLSI June 2010.
ASAD Workshop Saclay (CEA Irfu) November 25, AGET circuit: Application Information actar.
1 Programming of FPGA in LiCAS ADC for Continuous Data Readout Week 4 Report Tuesday 22 nd July 2008 Jack Hickish.
MADEIRA Valencia report V. Stankova, C. Lacasta, V. Linhart Ljubljana meeting February 2009.
The AGET chip Circuit overview, First data & Status
DAQ ACQUISITION FOR THE dE/dX DETECTOR
ASIC Skiroc 2 Digital part
A 12-bit low-power ADC for SKIROC
FEE for TPC MPD__NICA JINR
A General Purpose Charge Readout Chip for TPC Applications
VMM ASIC ― Status Report - April 2013 Gianluigi De Geronimo
ECAL Front-end development
Digital Interface inside ASICs & Improvements for ROC Chips
96-channel, 10-bit, 20 MSPS ADC board with Gb Ethernet optical output
KRB proposal (Read Board of Kyiv group)
A Low Power Readout ASIC for Time Projection Chambers in 65nm CMOS
Digital Acquisition of Analog Signals – A Practical Guide
PIC18F458 Analog-to-Digital
TPC electronics Atsushi Taketani
Status of SPIROC: Next generation of SPIROC
AVR – ATmega103(ATMEL) Architecture & Summary
Jean-Francois Genat – Herve Grabas Mary Heinz – Eric Oberla
Valter Bonvicini, Giulio Orzan, Nicola Zampa, Gianluigi Zampa
TOF read-out for high resolution timing
Presentation transcript:

1 ACTAR meeting – Santiago March 2008 Requirements Features required not available in standard ASICs for HEP: Auto-triggerable. Large dynamic range. Low noise. Multiple sampling ? : –For tracks with angles. –For common mode rejection Hess2, jv 2008

2 ACTAR meeting – Santiago March 2008 ALTRO For: The most advanced chip including A/D conversion On chip Baseline correction. Digital zero supression. External PA Against: Power 35mW/ch 16 ch./chips only. External PA. PASA treats only « cathod » signal polarity. Baseline correction limited.

3 ACTAR meeting – Santiago March 2008 Proposal from TU Munich For: Smart triggering. Digital zero supression. Against: Doesnot exist

4 ACTAR meeting – Santiago March 2008 AFTER cells SCA FILTER 100ns<tpeak<2us CSA 1 channel x72(76) 76 to 1 BUFFER Configuration Registers & Serial Interface 4-wire link ADC Test Test inputs 120fC<Cf<600fC Power SupplyReference Voltage Reference Current Power-On Reset AFTER CHIP SCA Controller W / R Mode CK Asic Spy Mode CSA;CR;SCAin MUX TH