MULTILAYER INTERCONNECTS

-CONNECTIONS - ISOLATIONS

METALS = INTERCONNECTIONS ON DIE / VIAS / INTERLAYER CONNECTIONS METALLIZATION = PROCESS OF DEPOSITING METAL LAYERS ON WAFER TYPES = Al, Cu, Au, Ti, W, Ta, Pd etc. METALLIZATION

REQUIREMENTS Low  < 4  cm Ag = 1.6  cm Cu = 1.7  cm Au = 2.2  cm Al = 2.7  cm R =  l/wh ; l=length, w=width, h=height wh=area

REQUIREMENTS Surface smoothness, hillock resistant Electromigration resistant Bondable Adhesion - to Si, SiO 2 - Al, Ti, Ti:W & TiN Corrosion resistant Non-contaminating - device/wafer/eqmnt

REQUIREMENTS Mechanically, electrically stable - withstand sintering,interlevel & passivation dielectric deposition -withstand oxidizing ambient -withstand normal operating conditions -withstand ordinary storage (stress voids)

REQUIREMENTS DEPOSITION -tightly controlled thickness -uniformity -particulate free ETCHABLE -anisotropically with hi S wrt subs. & mask

REQUIREMENTS STEP COVERAGE GOODTHIN SHADOWED

REQUIREMENTS REFLECTANCE - controllable for effective photolithography processing DEPOSITION -combination - multilayer -alloy form - tightly controllable -pure form - no reaction with gases in chamber - w/o incorporation of residual gases

REQUIREMENTS Low film stress Economic deposition & patterning - high throughput - equipment $ - purchase - maintenance - operating - high reliability & up-time - low complexity - no B.Eng/M.Eng/Ph.D

Al -DC Magnetron sputter & CVD -+pts - low  - adhesion to Si & SiO 2 - bonding - well characterized

Al --pts - low melting T ~660 0 C - low eutectic T with Si ~ C - forms 0 C - electromigration & corrosion - junction spiking

Al Solutions -hillocks - Ti, Cr, Ta layers sandwiched bet. Al layers - Ti:W layers above & below Al film - W selectively deposited on top & sidewalls of Al lines

Al Solutions -hillocks & electromigration - add Cu, Ti, Pd & Si-alloys -all problems =Al ALLOY / MULTILAYER Al STRUCTURE - alloys =  hi, (corrosion resistance, etchability & bondability) lo

Ti Magnetron Plasma Sputter & CVD Applications : silicides, nitridation, wetting layer & welding layer Low  Can form poly-Si G & S/D in Self- Aligned siLICIDE (salicide) process

Ti Junction spiking = Si dissolves in contact points = S/D areas ==> Al diffuses in Si ==> Al spikes n-Si p+ SiO 2

Ti Welding layer for W & Al-alloys - reduces contact R by scavenging O no WO 4 & Al 2 O 3 TiN - diffusion barrier for W plug & local interconnection ==> W diffuses in Si subs.

Ti W PSG Al-Cu Ti-Si 2 Ti TiN n+

W CVD Fill contact / via holes = plugs connecting metal & Si or between different metal lines better high aspect ratio contact holes / vias, than Al - W PVD- excellent step coverage - gap-fill capability

W CVD W  ~6-15 .cm compared to PVD Al:Cu  ~ .cm Adheres badly to SiO 2 - needs TiN Diffuses through SiO 2 - heavy metal contamination - needs TiN

Cu- new, better Seed sputter, then CVD, EPD +pts -Power consumption down, speed uP ==>  Cu <  Al -higher e-migration resistance ==> heavy

Cu - problems Poor adhesion to SiO 2 High diffusion rate with Si & SiO 2 - heavy metal contamination==device malfunction Difficult dry etch -dual damascene metallization-no metal etch ==> Cu used

Cu- dual damascene I Pre-clean prior to metallization - remove native oxide / ploymer -Ar sputter etch -metal at via bottom exposed -transfer to PVD under hi-vac

Cu - dual damascene II Barrier layer - to eliminate Cu diffusion into Si - Ta, TaN Cu seed layer - ~ nm -nucleation sites-no deposition/poor uniformity -ionized metal plasma-step coverage

-Cu lo-ionization E ==>vapour ionised easily off Ar flow=> Cu vapour Cu mfp ~ few thousand A>via depth ==> good bottom & side coverage & smooth film

Cu - dual damascene III Cu ECP=ECD=EPD - good for low-k -cathode holds wafer with conducting seal ring -immersed in H 2 SO 4 + CuSO 4 + additives -I flow from Cu-anode to cathode -Cu 2+ adsorb, nucleate & deposit seed / strike layer -liquid/solid surface tension of high aspect ratio via/trench pulls CuSO 4 - DIW rinse, spin dry, anneal 0 C, CMP

Ta; Co Ta - barrier layer prior to Cu deposition - prevent Cu diffusion via SiO 2 to Si Co - as a silicide - CoSi 2 - polycide G & local interconnection

METAL FILM-THICKNESS Al, Ti, TiN & Cu = opaque - reflectospectrometry unusable - destructive measurements -SEM - sample needs slicing, uniformity difficult - surface profiler Stage --> stylus Film thickness

METAL FILM - THICKNESS -non-destructive measurements - acoustic - thickness & uniformity SiO 2 TiN d =v s  t/2 ; v s =speed of sound in medium

METAL FILM THICKNESS Ultrathin TiN films ~transparent - reflectospctrometry 4pp - assuming resistivity constant across wafer

METAL FILM - UNIFORMITY 49 pt. measurement - 3  std. deviation non-uniformity = most common - sheet resistance / reflectivity measurements -production wafers use 5 / 9pts. - less t ==> less $

METAL FILM - STRESS Film - substrate material mismatch compressive & tensile - curvature Hi compression - hillocks - interlayer shorts Hi tensile - cracks / peels Stress = intrinsic / thermal -intrinsic = film density - plasma sputter - compressive -thermal = film/substrate thermal expansion rate mismatch

METAL FILM - REFLECTIVITY Constant reflectivity = stable metallization; change=process drifts Reflectivity =f(1/grain size, surface smoothness) Surface light reflectance = reflectivity, Si reference

METAL FILM - REFLECTIVITY Photolithography - incoming & reflected light = interference = standing wave==> affects resolution-wavy grooves For Al -AR coats, Al to Si reflectivity ~ %

SHEET RESISTANCE -monitor conducting thin-film deposition -uniformity / thickness measurement L A t w L R=  L/A==> of conductor =  L/(wt)==> of line Sheet resistance = for square; L=w ==>R s =  /t If uniform, size doesn’t matter, R1micron=R1in.

ISAOLTION = DIELECTRIC WANTED -low-k for f~20MHz - intermetal C low -hi breakdown field strength >5MV/cm -lo leakage with EF~5MV/cm -bulk  >10 15 .cm -lo surface conductance,  >10 15 .cm -impermeable to moisture

-exhibit lo stress, preferably compressive ~5x10 8 dynes/cm 2 ;tensile=crack -good adhesion bet. Al & dielect. -good adhesion bet. ILDs -stable up to C -easily etched -H permeable=>anealing in H 2 ambience -no incorporated charges / dipoles -no metallic impurities -non-reentrant coverages

-good thickness uniformity across wafer; wafer-wafer -doped oxides - good dopant uniformity across wafer; wafer-wafer -lo pinhole / particulate defect densities -no residual outgassing constituents

PMD SiO 2 best PMD layer in MOS ICs k SiN >k SiO2 & SiN cannot flow / reflow SiO 2 variants =PSG & BPSG; stress reliever