Nonlinear & Neural Networks LAB. CHAPTER 11 LATCHES AND FLIP-FLOPS 11.1Introduction 11.2Set-Reset Latch 11.3Gated D Latch 11.4Edge-Triggered D Flip-Flop 11.5S-R Flip-Flop 11.6J-K Flip-Flop 11.7T Flip-Flop 11.8Flip-Flop with Additional Inputs 11.9Summary

Nonlinear & Neural Networks LAB. Objectives 1.Explain in words the operation of S-R and gated D latches 2. Explain in words the operation of D, D-CE, S-R, J-K and T flip-flops 3. Make a table and derive the characteristic (next-state) equation for such latches and flip-flops. State any necessary restrictions on the input signals 4. Draw a timing diagram relating the input and output of such latches flip-flops 5. Show how latches and flip-flops can be constructed using gates. Analyze the operation of a flip-flop that is constructed of gates and latches

Nonlinear & Neural Networks LAB Introduction Fig Fig To construct a switching circuit has a memory, must introduce feedback to circuit  Unstable state  Stable state

Nonlinear & Neural Networks LAB Set-Reset Latch Fig Fig S=R=0 (Q=0)  S=1, R=0 S=R=0 (Q=1)  S=0, R=1

Nonlinear & Neural Networks LAB Set-Reset Latch Fig S-R Latch(cross-coupled structure) Fig Improper S-R Latch Operation (S=R=1; prohibited)

Nonlinear & Neural Networks LAB Set-Reset Latch Fig Timing Diagram for S-R Latch Table S-R Latch Operation Inputs not allowed

Nonlinear & Neural Networks LAB Set-Reset Latch Fig Map for Fig Switch Debouncing with an S-R Latch

Nonlinear & Neural Networks LAB Set-Reset Latch Fig Latch Inputs not allowed

Nonlinear & Neural Networks LAB Gated D Latch Figure Gated D Latch Figure Symbol and Truth Table for Gated Latch

Nonlinear & Neural Networks LAB Edge-Triggered D Flip-Flop Figure D Flip-Flops Truth table Figure Timing for D Flip-Flop (Falling-Edge Trigger)

Nonlinear & Neural Networks LAB Edge-Triggered D Flip-Flop Given FunctionFigure D Flip-Flop (Rising-Edge Trigger) Figure Setup and Hold Times for an Edge-Triggered D Flip-Flop

Nonlinear & Neural Networks LAB Edge-Triggered D Flip-Flop Figure Determination of Minimum Clock Period

Nonlinear & Neural Networks LAB S-R Flip-Flop Figure S-R Flip-Flop Operation summary : S=R=0 S=1, R=0 S=0, R=1 S=R=1 No state change Set Q to 1 (after active Ck edge) Reset Q to 0 (after active Ck edge) Not allowed Figure S-R Flip-Flop Implementation and Timing

Nonlinear & Neural Networks LAB J-K Flip-Flop Figure J-K Flip-Flop (Q Changes on the Rising Edge) Truth table and characteristic equation

Nonlinear & Neural Networks LAB J-K Flip-Flop Figure Master-Slave J-K Flip-Flop (Q Changes on Rising Edge)

Nonlinear & Neural Networks LAB T Flip-Flop Figure T Flip-Flop Figure Timing Diagram for T Flip-Flop (Falling-Edge Trigger)

Nonlinear & Neural Networks LAB T Flip-Flop Figure Implementation of T Flip-Flop

Nonlinear & Neural Networks LAB Flip-Flops with Additional Inputs Figure D Flip-Flop with Clear and Preset x x 0 0 x x 0 1 x x ,1, x 1 1 (not allowed) Q(no charge) Figure Timing Diagram for D Flip-Flop with Asynchronous Clear and Preset

Nonlinear & Neural Networks LAB Flip-Flops with Additional Inputs Figure D Flip-Flop with Clock Enable The MUX output : The characteristic equation :

Nonlinear & Neural Networks LAB Summary (S-R latch or flip-flop) (gated D latch) (D flip-flop) (D-CE flip-flop) (J-K flip-flop) (T flip-flop)