FPGA-Based System Design: Chapter 7 Copyright  2004 Prentice Hall PTR Topics n Bus interfaces. n Platform FPGAs.

FPGA-Based System Design: Chapter 7 Copyright  2004 Prentice Hall PTR Bus interfaces n Requirements: –High performance. –Variable signal environment. n Techniques: –Asynchronous logic. –Handshaking-oriented protocols.

FPGA-Based System Design: Chapter 7 Copyright  2004 Prentice Hall PTR Timing diagrams a b c stable 0 1 changing Timing constraint

FPGA-Based System Design: Chapter 7 Copyright  2004 Prentice Hall PTR Asynchronous logic n Distribute timing information with values. –No global clock. n Clock signal paths must have the same delay as data values.

FPGA-Based System Design: Chapter 7 Copyright  2004 Prentice Hall PTR Latching an asynchronous signal DQ adrs adrs_ready adrs

FPGA-Based System Design: Chapter 7 Copyright  2004 Prentice Hall PTR Asynchronous timing constraints n Must satisfy setup, hold times. adrs Setup time Hold time

FPGA-Based System Design: Chapter 7 Copyright  2004 Prentice Hall PTR Bus system design n Requirements: –Imposed by the other side of the system. n Constraints: –Imposed by this side of the system. ab requirements constraints

FPGA-Based System Design: Chapter 7 Copyright  2004 Prentice Hall PTR ba Views of the bus n Hardware: DQDQ Combinational logic

FPGA-Based System Design: Chapter 7 Copyright  2004 Prentice Hall PTR Views of bus system, cont’d. n Timing diagram: ba DQDQ Combinational logic x y xy

FPGA-Based System Design: Chapter 7 Copyright  2004 Prentice Hall PTR Bus protocols n Basic transaction: –four-cycle handshake. a b

FPGA-Based System Design: Chapter 7 Copyright  2004 Prentice Hall PTR Handshake machine n Each side is an FSM (possibly asynchronous): ab 01 Go ack enq 01 ack

FPGA-Based System Design: Chapter 7 Copyright  2004 Prentice Hall PTR Basic protocols n Handshake transmits data:

FPGA-Based System Design: Chapter 7 Copyright  2004 Prentice Hall PTR Box 1 logic

FPGA-Based System Design: Chapter 7 Copyright  2004 Prentice Hall PTR Box 2 logic

FPGA-Based System Design: Chapter 7 Copyright  2004 Prentice Hall PTR Bus timing t d1 = d stable t d2 = d not stable t c1 = c rises t c2 = c falls t ack1 = ack rises t 1 = t c1 - t d1 >= t r t 2 = t ack1 - t c1 >= t h t 3 = t c2 - t ack1 >= t h

FPGA-Based System Design: Chapter 7 Copyright  2004 Prentice Hall PTR Busses and systems n Microprocessor systems often have several busses running at different rates: CPU bridge mem I/O High-speed Low-speed

FPGA-Based System Design: Chapter 7 Copyright  2004 Prentice Hall PTR Basic signals in a bus

FPGA-Based System Design: Chapter 7 Copyright  2004 Prentice Hall PTR Bus characteristics n Physical –Connector size, etc. n Electrical –Voltages, currents, timing. n Protocol –Sequence of events.

FPGA-Based System Design: Chapter 7 Copyright  2004 Prentice Hall PTR Advanced transactions n Multi-cycle transfers: –Several values on one handshake. –May use implicit addressing.

FPGA-Based System Design: Chapter 7 Copyright  2004 Prentice Hall PTR PCI bus n Used for box-level system interconnect. n Two versions: –33 MHz. –66 MHz. n Supports advanced transactions.

FPGA-Based System Design: Chapter 7 Copyright  2004 Prentice Hall PTR PCI bus read

FPGA-Based System Design: Chapter 7 Copyright  2004 Prentice Hall PTR Multi-rate systems n Logic blocks running at different clock rates may communicate: –Multi-chip. –Single-chip. »Slow bus connects to fast logic. Logic 1Logic MHz33 MHz

FPGA-Based System Design: Chapter 7 Copyright  2004 Prentice Hall PTR Metastability n Registers capturing transitioning signals may take an arbitrarily long time to settle.

FPGA-Based System Design: Chapter 7 Copyright  2004 Prentice Hall PTR Resynchronization n Use cascaded registers to minimize the chance of using a metastable value. DQDQ ddout 

FPGA-Based System Design: Chapter 7 Copyright  2004 Prentice Hall PTR Platform FPGAs n Put all the logic for a system on one FPGA. n Requires large FPGAs plus: –Specialized logic: »I/O support; »memory interface. –CPUs.

FPGA-Based System Design: Chapter 7 Copyright  2004 Prentice Hall PTR Example: Virtex II Pro n Major features: –Large FPGA fabric. –High-speed I/O. –PowerPC.

FPGA-Based System Design: Chapter 7 Copyright  2004 Prentice Hall PTR Virtex II Pro High-speed I/O n Rocket I/O: –parallel/serial or serial/parallel transceiver. n Clock recovery circuitry. n Transceivers for multiple standards: Gigabit Ethernet, Fibre Channel, etc. n Programmable decoding features. n Interface to FPGA fabric.

FPGA-Based System Design: Chapter 7 Copyright  2004 Prentice Hall PTR Virtex II Pro CPUs n Up to 4 PowerPC 405s per chip: –5 stage pipe, static branch prediction, etc. n Separate instruction, data caches. n MMU. n Timers. n Scan-based debug support.

FPGA-Based System Design: Chapter 7 Copyright  2004 Prentice Hall PTR PowerPC CoreConnect

FPGA-Based System Design: Chapter 7 Copyright  2004 Prentice Hall PTR Altera Stratix n Combines FPGA fabric, memory blocks, multipliers.

FPGA-Based System Design: Chapter 7 Copyright  2004 Prentice Hall PTR Stratix DSP block