© imec 2004 1 Interconnect Width Selection for Deep Submicron Designs using the Table Lookup Method Mandeep Bamal, Evelyn Grossar, Michele Stucchi and.

Slides:

Advertisements

Similar presentations

Work in Progress --- Not for Publication 6 December Interconnect Working Group ITRS 2000 Lakeshore Hotel, Hsinchu, Taiwan, R.O.C. 6 December 2000.

Advertisements

Work in Progress --- Not for Publication DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference Interconnect Working Group ITRS 2004 Update.

ECE 424 – Introduction to VLSI

Design Rule Generation for Interconnect Matching Andrew B. Kahng and Rasit Onur Topaloglu {abk | rtopalog University of California, San Diego.

A Novel 3D Layer-Multiplexed On-Chip Network

-1- VLSI CAD Laboratory, UC San Diego Post-Routing BEOL Layout Optimization for Improved Time- Dependent Dielectric Breakdown (TDDB) Reliability Tuck-Boon.

ELEN 468 Lecture 261 ELEN 468 Advanced Logic Design Lecture 26 Interconnect Timing Optimization.

ECE 6466 “IC Engineering” Dr. Wanda Wosik

1 Interconnect Layout Optimization by Simultaneous Steiner Tree Construction and Buffer Insertion Presented By Cesare Ferri Takumi Okamoto, Jason Kong.

1 Worst-case Delay Analysis Considering the Variability of Transistors and Interconnects Takayuki Fukuoka, Tsuchiya Akira and Hidetoshi Onodera Kyoto University.

DARPA Assessing Parameter and Model Sensitivities of Cycle-Time Predictions Using GTX u Abstract The GTX (GSRC Technology Extrapolation) system serves.

Interconnect Optimizations. A scaling primer Ideal process scaling: –Device geometries shrink by  = 0.7x) Device delay shrinks by  –Wire geometries.

EE4271 VLSI Design Interconnect Optimizations Buffer Insertion.

Interconnect Optimizations. A scaling primer Ideal process scaling: –Device geometries shrink by S  = 0.7x) Device delay shrinks by s –Wire geometries.

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 14: Interconnects Prof. Sherief Reda Division of Engineering, Brown University.

04/09/02EECS 3121 Lecture 25: Interconnect Modeling EECS 312 Reading: 8.3 (text), 4.3.2, (2 nd edition)

Interconnect Optimizations

Lecture #25a OUTLINE Interconnect modeling

On-Line Adjustable Buffering for Runtime Power Reduction Andrew B. Kahng Ψ Sherief Reda † Puneet Sharma Ψ Ψ University of California, San Diego † Brown.

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 22: Material Review Prof. Sherief Reda Division of Engineering, Brown University.

University of Toronto Pre-Layout Estimation of Individual Wire Lengths Srinivas Bodapati (Univ. of Illinois) Farid N. Najm (Univ. of Toronto)

Effects of Global Interconnect Optimizations on Performance Estimation of Deep Sub-Micron Design Yu (Kevin) Cao 1, Chenming Hu 1, Xuejue Huang 1, Andrew.

Circuit Performance Variability Decomposition Michael Orshansky, Costas Spanos, and Chenming Hu Department of Electrical Engineering and Computer Sciences,

Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 9.1 EE4800 CMOS Digital IC Design & Analysis Lecture 9 Interconnect Zhuo Feng.

Ryan Kastner ASIC/SOC, September Coupling Aware Routing Ryan Kastner, Elaheh Bozorgzadeh and Majid Sarrafzadeh Department of Electrical and Computer.

ELEN 468 Lecture 271 ELEN 468 Advanced Logic Design Lecture 27 Interconnect Timing Optimization II.

Statistical Gate Delay Calculation with Crosstalk Alignment Consideration Andrew B. Kahng, Bao Liu, Xu Xu UC San Diego

Effects of Global Interconnect Optimizations on Performance Estimation of Deep Sub-Micron Design Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Sudhakar.

THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis.

Noise and Delay Uncertainty Studies for Coupled RC Interconnects Andrew B. Kahng, Sudhakar Muddu † and Devendra Vidhani ‡ UCLA Computer Science Department,

ECE 424 – Introduction to VLSI Design

A Methodology for Interconnect Dimension Determination By: Jeff Cobb Rajesh Garg Sunil P Khatri Department of Electrical and Computer Engineering, Texas.

Determining the Optimal Process Technology for Performance- Constrained Circuits Michael Boyer & Sudeep Ghosh ECE 563: Introduction to VLSI December 5.

Research on Analysis and Physical Synthesis Chung-Kuan Cheng CSE Department UC San Diego

Comparison of various TSV technology

Kwangsoo Han, Andrew B. Kahng, Hyein Lee and Lutong Wang

1 Interconnect and Packaging Lecture 8: Clock Meshes and Shunts Chung-Kuan Cheng UC San Diego.

Detailed Routing: New Challenges

Scaling II Mohammad Sharifkhani. Reading Textbook I, Chapter 2 Textbook II, Section 3.5, Section 4.5.3, Section 5.6.

Text Book: Silicon VLSI Technology Fundamentals, Practice and Modeling Authors: J. D. Plummer, M. D. Deal, and P. B. Griffin Class: ECE 6466 “IC Engineering”

Proposed Roadmap Tables on STRJ-WG1

1 Interconnect/Via. 2 Delay of Devices and Interconnect.

Routing Tree Construction with Buffer Insertion under Obstacle Constraints Ying Rao, Tianxiang Yang Fall 2002.

ADVANCED HIGH DENSITY INTERCONNECT MATERIALS AND TECHNIQUES DIVYA CHALLA.

Introduction to Clock Tree Synthesis

Chapter 4: Secs ; Chapter 5: pp

Caltech CS184 Winter DeHon 1 CS184a: Computer Architecture (Structure and Organization) Day 6: January 22, 2003 VLSI Scaling.

EE 587 SoC Design & Test Partha Pande School of EECS Washington State University

Design For Manufacturability in Nanometer Era

Interconnect Driver Design for Long Wires in FPGAs Edmund Lee University of British Columbia Electrical & Computer Engineering MASc Thesis Presentation.

-1- Delay Uncertainty and Signal Criticality Driven Routing Channel Optimization for Advanced DRAM Products Samyoung Bang #, Kwangsoo Han ‡, Andrew B.

Interconnect Driver Design for Long Wires in FPGAs Edmund Lee, Guy Lemieux & Shahriar Mirabbasi University of British Columbia, Canada Electrical & Computer.

14/2/20041 Interconnect-Power Dissipation in a Microprocessor N. Magen, A. Kolodny, U. Weiser, N. Shamir Intel corporation® Technion - Israel Institute.

14 February, 2004SLIP, 2004 Self-Consistent Power/Performance/Reliability Analysis for Copper Interconnects Bipin Rajendran, Pawan Kapur, Krishna C. Saraswat.

CARBON NANOTUBES (A SOLUTION FOR IC INTERCONNECT) By G. Abhilash 10H61D5720.

Temperature Aware Circuits A Temperature Sensor in the Interconnect Layer Matthew Lindsey.

Oleg Petelin and Vaughn Betz FPL 2016

Circuit characterization and Performance Estimation

The Interconnect Delay Bottleneck.

Crosstalk If both a wire and its neighbor are switching at the same time, the direction of the switching affects the amount of charge to be delivered and.

Topics Driving long wires..

Defect Tolerance for Nanocomputer Architecture

Jason Cong, David Zhigang Pan & Prasanna V. Srinivas

Signal Propagation Along Interconnects

Summary Current density in a signal line was estimated, based on the simple circuit shown in Fig.1. This circuit is scaled down according to ITRS 2003.

Puneet Gupta1 , Andrew B. Kahng1 , Youngmin Kim2, Dennis Sylvester2

Technology scaling Currently, technology scaling has a threefold objective: Reduce the gate delay by 30% (43% increase in frequency) Double the transistor.

Applications of GTX Y. Cao, X. Huang, A.B. Kahng, F. Koushanfar, H. Lu, S. Muddu, D. Stroobandt and D. Sylvester Abstract The GTX (GSRC Technology Extrapolation)

by Yi Zhao CMPE640 ITRS presentation Fall 2005

Jason Cong, David Zhigang Pan & Prasanna V. Srinivas

Presentation transcript:

© imec Interconnect Width Selection for Deep Submicron Designs using the Table Lookup Method Mandeep Bamal*, Evelyn Grossar*, Michele Stucchi and Karen Maex* IMEC, Leuven, Belgium * Also at Department of Electrical Engineering (ESAT), Katholieke Universiteit Leuven, Belgium SLIP’2004, Paris February,2004

© imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris2 Introduction Backend Technology N + 1 Metal Dielectric Silicon N N : Tech. Node  More Functions per area  Less Cost per function

© imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris3 Interconnect Delay W. Wu, R. Jonckheere, M. Stucchi, H. Struyf, Z. Tőkei, I. Vervoort, I. Vos, F. Iacopi, and K. Maex, Studies on Resistivity of Narrow Cu Interconnects, Proceedings of Advanced Metallization Conference, pp , (San Diego, October 2002) Optical E-beam ITRS RC trends in ITRS 2003

© imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris4 Technology Issues S’~10nm! ‘Electrical equivalent sidewall damage’ F. Iacopi, M. Stucchi, O. Richard and K. Maex, ”Electrical Equivalent Sidewall Damage in Patterned Low-k Dielectrics”,to appear in Electrochemical and Solid-State Letters, 2004.

© imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris5 Interconnect Exploration Metal Dielectric Silicon NNNN Let us assume that scaling continues in spite of DSM issues NN Hard to improve material properties Window of freedom exists for interconnect exploration Power Delay Width and Height exploration for constant pitch

© imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris6 Interconnect Width Sizing  Width Sizing [ Lee2000,Alpert2001,Cong2002,Jiang2001 ]  Decreasing the wire width progressively from source to sink.(TWS)  Multiple Width Sizing (MWS or TWS)  Uniform Width Sizing (UWS) Driver Load Wire widthWire position Driver Load Driver Load Problems with routing

© imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris7 Interconnect Width Selection by Table Lookup Method Driver Interconnect 2 n 1 SlewInverterRN AdderC Buffer Mux. Length Type of load

© imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris8 4-D Lookup Table Variable slew Driver Variable C2 R Variable C1 C2C1 Variable R R = 0.48Rint C1 = 1/6Cint C2 = 5/6Cint + C L O’Brien/Savarino pi Model Pre- Characterized Delay and Power Table R C1 C2 slew Delay Power

© imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris9 Exploration Methodology (Case Study-1)

© imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris10 Circuit Example (2 pin net) Assumptions  Exploration for 45 nm node  Length information obtained by using rent’s rule for a simple isotropic model of an IC (a priori length information)  Analysis done for average wire length in 2 nd layer (440 um)  Driver and load both are 4x inverters  45nm BSIM4 model card used [1]  One width per layer assumed  T A  B and Total power dissipation were calculated Driver Interconnect Load A B [1] 4x 100 psec T10.5p T20.4p T30.3p T40.2p T50.1p width

© imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris11 Exploration of width for optimizing delay T10.5p T20.4p T30.3p T40.2p T50.1p

© imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris12 SI Analysis Vt T10.5p T20.4p T30.3p T40.2p T50.1p

© imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris13 Power vs. Delay Normalized w.r.t. T1 T10.5p T20.4p T30.3p T40.2p T50.1p

© imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris14 Including Buffer Sizing Normalized w.r.t. T1 and 4x Driver Interconnect Load A B 4x100 psec T10.5p T20.4p T30.3p T40.2p T50.1p 4x 1x 2x 4x 8x

© imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris15 Power-Delay Trade off’s Normalized w.r.t. T1 and 4x T10.5p T20.4p T30.3p T40.2p T50.1p

© imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris16 Local Interconnects ( length = 40 um) Normalized w.r.t. T1 and 4x T10.5p T20.4p T30.3p T40.2p T50.1p

© imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris17 Global Interconnects (length = 800 um) Normalized w.r.t. T1 and 4x T10.5p T20.4p T30.3p T40.2p T50.1p

© imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris18 Conclusions  Exploration can be done for interconnect dimensions  Informed choice for interconnect dimensions  Local Interconnects (very short wires…)  Not much Trade off is possible by width-only exploration  Smallest width is the best solution for constant pitch in context of power and delay optimization  Intermediate Interconnects  Significant Trade off can be made between delay and power  Global Wires  Dissipation can be traded for reducing the delay  Simultaneous buffer sizing and wire sizing is the best option  Future work  Variable pitch and height exploration  Better Signal Integrity evaluation models  Effect on area

© imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris19 Thank you! questions