1. Detailed Routing: New Challenges

2. Detailed Routing: New challenges
Manufacturers use different wire widths
Vias connecting wires of different widths
 block additional routing resources on the layer with the smaller wire pitch

3. Detailed Routing: New challenges
Representative layer stacks for 130 nm - 32 nm technology nodes U2 W1 U1 E2 E2 E1 E1 B3 E1 B3 B2 B2 B2 B3 B1 M6 B1 B2 C2 B1 M5 M5 B1 C1 M5 M4 M4 M4 M4 M4 M3 M3 M3 M3 M3
© 2011 Springer Verlag M2 M2 M2 M2 M2 M1 M1 M1 M1 M1
130 nm
90 nm
65 nm
45 nm
32 nm

4. Detailed Routing: New challenges
Manufacturing yield: a key concern in detailed routing
Redundant vias and wiring segments as backups (via doubling and non-tree routing)
Manufacturability constraints (design rules) become more restrictive  complicate detailed routing
Example: design rules specify minimum allowed spacing between wires and vias depending on their widths and proximity to wire corners.
Example: Recent spacing rules take into account multiple neighboring polygons.

5. Via Doubling

6. Detailed Routing: New challenges
Detailed routers must account for manufacturing rules and the impact of manufacturing faults
Via defects/performance degradation (from misalignments):
Via doubling during or after detailed routing
Area penalty
Interconnect defects:
Non-tree routing: Add redundant wires to already routed nets (postprocess)
Antenna-induced defects:

7. Antenna Effect Recent DFM Issue
Long metal lines and vias introduce antenna violations.
Conductor layers fabricated from lowest layer to highest layer.
The etch process builds up the electrical charges on metal layers.
These charges cause a high voltage spike, which may destroy the gates connected to the metals.

8. Antenna Effect A long line connected to gate only can cause failure
Not a problem after chip is complete since every net has at least one driver
Driver (diffusion)
Load (poly) M1 M2
But, we can have a problem during manufacturing
Here is the same net after M1 is built, but not yet M2
Driver (diffusion)
Load (poly) M1

9. Antenna Effect
Antenna violation
Diffusion
Sink 1
Sink 2
©[Wu]

10. Antenna Effect Antenna Violations: Metal area antenna rule:
the maximum limit to the ratio of the metal line area to the connected gates area.
R1 = Am / (W.L)

11. Antenna Rules
Violations to the above antenna rules in every metal layer have to be fixed before the chip tapeout.
Each metal layer may have various upper limit rules based on the process specifications.
0.18 (0.13) um technology: the maximum length of an “antenna” wire ≈ 500 um (20 um).
Process-Induced Damage Rules (otherwise known as “Antenna Rules”)-
General Requirements.

12. Antenna Avoidance Jumper Insertion:
Router inserts jumpers for long metals from low-level metals to upper-level layers.
The jump cuts the long metals in the low-level layers to disconnected pieces.
based on the fact that wire segments on top routing layers are normally fabricated at the end
Antenna violation
Diffusion
Gate
Jumper insertion
Diffusion
Gate

13. Antenna Avoidance Jumper Insertion: Disadvantage:
jumpers introduce extra vias
 Degrade both manufacturing yield and circuit timing performance
Jia Wang, Hai Zhou, “Optimal Jumper Insertion for
Antenna Avoidance under Ratio Upper-Bound,” DAC 2006.

14. Antenna Avoidance Diode Insertion: Disadvantages:
Place and route design adds the PN junction diodes to the unused area of the chip.
Connected to the wire segment.
Leaks the current to the ground when a high voltage spike occurs.
Disadvantages:
Depends on placement space
Diodes present extra capacitive load to the signal nets they are attached to.

15. Antenna Avoidance Layer Assignment:
Reduce antenna length by layer assignment.
Antenna violation
Diffusion
Gate
Jumper insertion
Diffusion
Gate
Layer assignment
Diffusion
Gate
Di Wu, Jiang Hu and Rabi Mahapatra, “Coupling Aware Timing
Optimization and Antenna Avoidance in Layer Assignment,” ISPD 2005.