ARM CPUs By: Team 2

ARM OS’s Windows CE family Windows 8 iOS webOS – Formerly called Palm Linux – Android – ChromeOS – Ubuntu

RISC vs. CISC RISC: – Simple instructions – More register memory CISC: – Complex instructions – Less register memory Recently Mac moved from RISC to CISC, Microsoft on the other hand is supporting both CISC RISC

Cache Physically-Indexed and Physically-Tagged (PIPT) (Physical cache) 32KB 2-way set-associative (Access Method) Fixed line length of 64 bytes ARM Cache and Write Buffer Organization Volatile Memory Stallings, William. "Cache Memory." Computer Organization and Architecture: Designing for Performance. Upper Saddle River, NJ: Prentice Hall, Print.

Cache (continued) Processor Speed Range

Cortex A15 Word Size: – 32-bit Register Size – Uniform 16 x 32-bit Register File Address BUS Size: – 40 bits RAM Addressable: – Up to 1TB Clock Speed – 35,000 MIPS at 2.5 GHz Data BUS Size: – 32-bit Number and Type of Instructions: – Type: A64 – # of Instructions: 32 bit Cache

Cache (continued) "Meet ARM's Cortex A15: The Future of the IPad, and Possibly the Macbook Air | Cloudline | Wired.com." Wired.com. Conde Nast Digital. Web. 10 Apr

Works Cited "ARM Information Center." Web. 09 Apr "Cortex-A Series." - ARM. Web. 09 Apr "RISC vs. CISC." WWW-CS-FACULTY & STAFF Home Page (12-Apr-1995). Web. 09 Apr Stallings, William. "Cache Memory." Computer Organization and Architecture: Designing for Performance. Upper Saddle River, NJ: Prentice Hall, Print. "Meet ARM's Cortex A15: The Future of the IPad, and Possibly the Macbook Air | Cloudline | Wired.com." Wired.com. Conde Nast Digital. Web. 10 Apr