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Computer Structure S.Abinash 11/29/2018 445_02
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Computer Functional Units
Processor Input Arithmetic & Logic Memory Output Control 11/29/2018 445_02
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Processor and Memory Processor MAR - Memory Address Register
MDR Control PC R0 R1 IR . . . ALU Rn-1 Processor MAR - Memory Address Register MDR - Memory Data Register PC - Program Counter IR - Instruction Register 11/29/2018 445_02
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Computer Instructions
Assembly Language MOVE NUM1,R1 MOVE #1,R2 ADD #1,R1 ADD R1,R2 Register Transfer Notation R1 [NUM1] R2 1 R1 1 + [R1] R2 [R1] + [R2] 11/29/2018 445_02
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Example Instruction Fetch Execute MOVE NUM1,R1 MAR [PC]
PC [PC] + 1 MDR [MEM([MAR])] IR [MDR] Execute MAR NUM1 MDR [MEM([MAR])] R1 [MDR] 11/29/2018 445_02
![Example Instruction Fetch Execute MOVE NUM1,R1 MAR [PC]](http://slideplayer.com/slide/14894293/91/images/5/Example+Instruction+Fetch+Execute+MOVE+NUM1%2CR1+MAR+%EF%82%AC+%5BPC%5D.jpg "PC [PC] + 1. MDR [MEM([MAR])] IR [MDR] Execute. MAR NUM1. MDR [MEM([MAR])] R1 [MDR] 11/29/ _02.")
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Another Example Fetch Execute ADD #1,R1 MAR [PC] PC [PC] + 1
MDR [MEM([MAR])] IR [MDR] Execute R1 1 + [R1] 11/29/2018 445_02
![Another Example Fetch Execute ADD #1,R1 MAR [PC] PC [PC] + 1](http://slideplayer.com/slide/14894293/91/images/6/Another+Example+Fetch+Execute+ADD+%231%2CR1+MAR+%EF%82%AC+%5BPC%5D+PC+%EF%82%AC+%5BPC%5D+%2B+1.jpg "MDR [MEM([MAR])] IR [MDR] Execute. R1 1 + [R1] 11/29/ _02.")
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Single-Bus Structure Input Output Memory Processor 11/29/2018 445_02
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Single-Bus Architecture (HW1)
MAR MEM MDR Y A B ALU R Z 11/29/2018 445_02
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Single-Bus Architecture (HW3)
6 6 MAR 6 PC MEM 1 MDR 2 IR 1 2 6 MUX MUX 2 Y 1 1 REGS A B ALU R Z 11/29/2018 445_02
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Design Project Architecture
BUS A BUS B BUS C 6 PC IR 1 1 2 A1 A2 1 REGS 2 2 MUX A ALU R B NZVC 2 MDR 2 3 1 6 MAR MEM 11/29/2018 445_02
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System Software Compiler Assembler Text Editor Operating System
High-level Language Machine Language Assembler Assembly Language Machine Language Text Editor Keyboard Input File Operating System Control Sharing & Interaction Assign & Manage Resources Memory Disk Space Handle I/O 11/29/2018 445_02
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Memory Performance Main Processor Memory Cache Memory 11/29/2018
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Processor Clock Period (P) Rate (R) R = 1/P 1 GHz = 1/1ns CLK
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Performance Equation Processor Execution Time (T)
Number of Machine Language Instructions (N) Average Steps per Machine Instruction (S) Clock Rate (R) Performance Measurement (Benchmarking) 11/29/2018 445_02
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Pipelining F1 E1 I1 F2 E2 I2 F3 E3 I3 Sequential Execution F1 E1 I1 F2
Pipelined Execution 11/29/2018 445_02
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Parallel Processing Parallel Execution Multiprocessors Multicomputers
Superscalar Multiprocessors Shared-Memory Multicomputers Message-Passing 11/29/2018 445_02
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CISC vs RISC Complex Instruction Set Computers (CISC)
Smaller N Larger S Reduced Instruction Set Computers (RISC) Larger N Smaller S Easier to Pipeline 11/29/2018 445_02
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