1 COMP541 More on State Machines and Video Scanout Montek Singh Feb 13, 2007

2Outline  Look at Verilog coding practices  Types of state machines  How to generate video signal

3 Good Verilog Practices  Best to use single clock for all FFs Make all signals synchronous Make all signals synchronous Avoids “weird” and frustrating problems Avoids “weird” and frustrating problems  Multiple modules Tested individually Tested individually  One module per file Just to make it easier to follow and test Just to make it easier to follow and test

4 Assignment (of signals)  Continuous  Procedural Note there are two uses for always Note there are two uses for always To generate FFs and latches (plus gates) To generate FFs and latches (plus gates) Combinational only Combinational only  Latter does not introduce unnecessary FFs If synthesizer detects all possibilities covered (i.e. no state) If synthesizer detects all possibilities covered (i.e. no state)  Look at the synthesizer log

5 Procedural Assignment 1 module C2(output reg C = 0, input A, input B); (A or B) case ({A, B}) 2'b11: C <= 1; default: C <= 0; endcaseendmodule  Schematic next page

6Schematic  LUT is a look-up table  Double clicking it shows

7 Procedural Assignment 2 module C1(output reg C = 0, input A, input B); (A or B) begin if(A == 1 && B == 1) C <= 1; endendmodule  Synthesizer now says WARNING:Xst:737 - Found 1-bit latch for signal. WARNING:Xst: The value init of the FF/Latch C hinder the constant cleaning in the block C1.

8Schematic  LDE is latch  Small box is clock driver

9 In fact…  If I change the INIT of C like it says output reg C = 1 output reg C = 1  Synthesizer says INFO:Xst: Contents of register in unit never changes during circuit operation. The register is replaced by logic. INFO:Xst: Contents of register in unit never changes during circuit operation. The register is replaced by logic.

10Schematic module C1(output reg C = 1, input A, input B); (A or B) begin if(A == 1 && B == 1) C <= 1; endendmodule

11 Types of state machine  Try to explain what synthesizer is doing Read the messages on the console Read the messages on the console

12 Example State Machine  From XST manual Small error Small error ~x1

13 One Always Block (simplified – see handout) clk) begin case (state) case (state) s1: if (x1 == 1'b1) begin s1: if (x1 == 1'b1) begin state <= s2; outp <= 1'b1; state <= s2; outp <= 1'b1; end end else begin else begin state <= s3; outp <= 1'b0; state <= s3; outp <= 1'b0; end end s2: begin state <= s4; outp <= 1'b1; state <= s4; outp <= 1'b1; end end s3: begin s3: begin state <= s4; outp <= 1'b0; state <= s4; outp <= 1'b0; end end s4: begin s4: begin state <= s1; outp <= 1'b0; state <= s1; outp <= 1'b0; end end endcase endcaseend ~x1

14 Synthesis Output Synthesizing Unit. Related source file is "v_fsm_1.v". Related source file is "v_fsm_1.v". Found finite state machine for signal. Found finite state machine for signal | States | 4 | | States | 4 | | Transitions | 5 | | Transitions | 5 | | Inputs | 1 | | Inputs | 1 | | Outputs | 4 | | Outputs | 4 | | Clock | clk (rising_edge) | | Clock | clk (rising_edge) | | Reset | reset (positive) | | Reset | reset (positive) | | Reset type | asynchronous | | Reset type | asynchronous | | Reset State | 00 | | Reset State | 00 | | Power Up State | 00 | | Power Up State | 00 | | Encoding | automatic | | Encoding | automatic | | Implementation | LUT | | Implementation | LUT | Found 1-bit register for signal. Found 1-bit register for signal. Summary: Summary: inferred 1 Finite State Machine(s). inferred 1 D-type flip-flop(s).

15 Split Output Off  Separate always for outp

16 Code (see handout for full) clk) case (state) case (state) s1: if (x1 == 1'b1) s1: if (x1 == 1'b1) state <= s2; state <= s2; else else state <= s3; state <= s3; s2: state <= s4; s2: state <= s4; s3: state <= s4; s3: state <= s4; s4: state <= s1; s4: state <= s1; endcase endcase case (state) s1: outp = 1'b1; s1: outp = 1'b1; s2: outp = 1'b1; s2: outp = 1'b1; s3: outp = 1'b0; s3: outp = 1'b0; s4: outp = 1'b0; s4: outp = 1'b0; endcase endcase

17 Synthesis (no latch) Synthesizing Unit. Related source file is "v_fsm_2.v". Related source file is "v_fsm_2.v". Found finite state machine for signal. Found finite state machine for signal | States | 4 | | States | 4 | | Transitions | 5 | | Transitions | 5 | | Inputs | 1 | | Inputs | 1 | | Outputs | 1 | | Outputs | 1 | | Clock | clk (rising_edge) | | Clock | clk (rising_edge) | | Reset | reset (positive) | | Reset | reset (positive) | | Reset type | asynchronous | | Reset type | asynchronous | | Reset State | 00 | | Reset State | 00 | | Power Up State | 00 | | Power Up State | 00 | | Encoding | automatic | | Encoding | automatic | | Implementation | LUT | | Implementation | LUT | Summary: Summary: inferred 1 Finite State Machine(s). Unit synthesized.

18 Textbook Uses 3 always Blocks

19 Three always Blocks clk) clk) begin begin state <= next_state; end end or x1) or x1) begin begin case (state) case (state) s1: if (x1==1'b1) s1: if (x1==1'b1) next_state = s2; next_state = s2; else else next_state = s3; next_state = s3; s2: next_state = s4; s2: next_state = s4; s3: next_state = s4; s3: next_state = s4; s4: next_state = s1; s4: next_state = s1; endcase endcase end end begin begin case (state) case (state) s1: outp = 1'b1; s1: outp = 1'b1; s2: outp = 1'b1; s2: outp = 1'b1; s3: outp = 1'b0; s3: outp = 1'b0; s4: outp = 1'b0; s4: outp = 1'b0; endcase endcase end end

20 Synthesis (again, no latch) Synthesizing Unit. Related source file is "v_fsm_3.v". Related source file is "v_fsm_3.v". Found finite state machine for signal. Found finite state machine for signal | States | 4 | | States | 4 | | Transitions | 5 | | Transitions | 5 | | Inputs | 1 | | Inputs | 1 | | Outputs | 1 | | Outputs | 1 | | Clock | clk (rising_edge) | | Clock | clk (rising_edge) | | Reset | reset (positive) | | Reset | reset (positive) | | Reset type | asynchronous | | Reset type | asynchronous | | Reset State | 00 | | Reset State | 00 | | Power Up State | 00 | | Power Up State | 00 | | Encoding | automatic | | Encoding | automatic | | Implementation | LUT | | Implementation | LUT | Summary: Summary: inferred 1 Finite State Machine(s). Unit synthesized.

21 My Preference  The one with 2 always blocks  Less prone to error than 1 always  Easy to visualize the state transitions

22 State Encoding  So far we’ve used binary encoding  Not necessarily best XST chooses one to minimize hardware XST chooses one to minimize hardware  Can change by right-clicking Synthesize-XST  Possible encodings next slides

23 Gray Code (synthesis output) ============================================================ * Advanced HDL Synthesis * ============================================================ Analyzing FSM for best encoding. Optimizing FSM on signal with gray encoding State | Encoding State | Encoding | | | | | | | |

24 One-Hot Encoding Optimizing FSM on signal with one- hot encoding State | Encoding State | Encoding | | | | | | | | Hmmm, state register grew. What’s up?

25 Safe Implementation Mode “XST can add logic to your FSM implementation that will let your state machine recover from an invalid state. If during its execution, a state machine gets into an invalid state, the logic added by XST will bring it back to a known state, called a recovery state. This is known as Safe Implementation mode.” from XST manual “XST can add logic to your FSM implementation that will let your state machine recover from an invalid state. If during its execution, a state machine gets into an invalid state, the logic added by XST will bring it back to a known state, called a recovery state. This is known as Safe Implementation mode.” from XST manual Tuesday’s counter

26 How Do Monitors Work?  Origin is TV, so let’s look at that LCDs work on different principle, but all signaling still derived from TV of 1940s LCDs work on different principle, but all signaling still derived from TV of 1940s  Relies on your brain to do two things Integrate over space Integrate over space Integrate over time Integrate over time

27 Many Still Images  Video (and movies) a series of stills  If stills go fast enough your brain interprets as moving imagery Hz or more to not see flicker Hz or more to not see flicker  In fact, even single “still” image displayed over time

28 Cathode Ray Tube From wikipedia:

29 Deflection Coils

30 Simple Scanning TV  Electron beam scans across  Turned off when Scanning back to the left (horizontal retrace) Scanning back to the left (horizontal retrace) Scanning to the top (vertical retrace) Scanning to the top (vertical retrace)

31Scanning  TVs use interlacing Every other scan line is swept per field Every other scan line is swept per field Two fields per frame (30Hz) Two fields per frame (30Hz) Way to make movement less disturbing Way to make movement less disturbing  Computers use progressive scan Whole frame refreshed at once Whole frame refreshed at once 60Hz or more, 72Hz looks better 60Hz or more, 72Hz looks better

32Color  Three colors of phosphor  Beams hit each  Black – beam off  White – all on Picture is a bit misleading. Mask (or aperture grill) ensures beams hit only correct color phosphor.

33Aside  Frustrated with Verilog  See what to do to relieve stress  Educational too

34 VGA Signaling  RGB and two synchronization pulses, horizontal and vertical

35 VGA Timing  You supply two pulses, hsync and vsync, that let the monitor lock onto timing  One hsync per scan line  One vsync per frame Image from dell.com

36 Horizontal Timing Terms  hsync pulse  Back porch (left side of display)  Active Video Video should be blanked (not sent) at other times Video should be blanked (not sent) at other times  Front porch (right side) Picture not accurate for our case; just for illustration. Video and HSYNC not on same wire

37 Horizontal Timing 640 Horizontal Dots Horiz. Sync Polarity NEG Scanline time (A) us Sync pulse length (B) 3.77 us Back porch (C) 1.89 us Active video (D) us Front porch (E) 0.94 us Image from This diagram shows video as a digital signal. It’s not – video is an analog level.

38 Vertical Timing (note ms, not us) Vert. Sync Polarity NEG Vertical Frequency 60Hz Total frame time (O) ms Sync length (P) 0.06 ms Back porch (Q) 1.02 ms Active video (R) ms Front porch (S) 0.35 ms

39 Timing as Pixels  Easiest to derive all timing from single-pixel timing  How “long” is a pixel? Active video / number of pixels Active video / number of pixels us / 640 = 39.32ns us / 640 = 39.32ns Conveniently close to 25 MHz – just use that Conveniently close to 25 MHz – just use that Actual VESA spec is MHz Actual VESA spec is MHz

40Standards  640 x 480 (sometimes x 60Hz) is “VGA”  I’ll have spec sheets in lab  You can try for 800x600 at 60 Hz (40 MHz exactly)  or 800x600 at 72 Hz (50 MHz exactly)  Note that some standards have vsync and hsync positive true, some negative true – choose correct one

41 Color Depth  Voltage of each of RGB determines color  2-bit color here (4 shades)  Turn all on for white

42 What To Do Friday  Make Verilog module to generate hsync, vsync, horizontal count, vertical count, and signal to indicate active video hsync, vsync, horizontal count, vertical count, and signal to indicate active video  Use higher-level module to drive RGB using counts gated by active Just do something simple; need to meet 25MHz constraint Just do something simple; need to meet 25MHz constraint  Later will use memory addressed by counts to make terminal

43 What do you Need for VGA?  Think first Need counter(s)? Need counter(s)? Will you need a state machine? Will you need a state machine?  Sketch out a design Block diagram Block diagram  Go over them individually in lab  Keep in Mind Verilog has these operators Verilog has these operators ==,, = ==,, =

44 VGA Links  VGA Timing  Code (more complex than you want)  Interesting Liquid Crystals by S. Chandrasekhar, Cambridge Univ. Press Liquid Crystals by S. Chandrasekhar, Cambridge Univ. Press