1. COMP541 State Machines
Montek Singh
Feb 4, 2010

2. Topics More advanced Verilog State Machines
How to design machines that go through a sequence of events
Basically close this loop

3. First Topic
More Verilog…

4. Hierarchy
module and3(input a, b, c, output y); assign y = a & b & c; endmodule
module inv(input a, output y); assign y = ~a; endmodule
module nand3(input a, b, c
output y);
wire n1; // internal signal
and3 andgate(a, b, c, n1); // instance of and3
inv inverter(n1, y); // instance of inverter
endmodule

5. Internal Variables
module fulladder(input a, b, cin, output s, cout); wire p, g; // internal assign p = a ^ b; assign g = a & b; assign s = p ^ cin; assign cout = g | (p & cin); endmodule

6. Bitwise Operators (we have used)
module gates(input [3:0] a, b,
output [3:0] y1, y2, y3, y4, y5);
assign y1 = a & b; // AND
assign y2 = a | b; // OR
assign y3 = a ^ b; // XOR
assign y4 = ~(a & b); // NAND
assign y5 = ~(a | b); // NOR
endmodule
// single line comment
/*…*/ multiline comment

7. Reduction Operators
module and8(input [7:0] a, output y); assign y = &a; // &a is much easier to write than // assign y = a[7] & a[6] & a[5] & a[4] & // a[3] & a[2] & a[1] & a[0]; endmodule

8. Precedence ~ NOT *, /, % mult, div, mod +, - add,sub
Highest ~
NOT
*, /, %
mult, div, mod
+, -
add,sub
<<, >>
shift
<<<, >>>
arithmetic shift
<, <=, >, >=
comparison
==, !=
equal, not equal
&, ~&
AND, NAND
^, ~^
XOR, XNOR
|, ~|
OR, XOR ?:
ternary operator
Lowest

9. Numbers Format: N'Bvalue N = number of bits, B = base
N'B is optional but recommended (default is decimal)
Number
# Bits
Base
Decimal Equivalent
Stored
3’b101 3
binary 5
101
‘b11
unsized
00…0011
8’b11 8
8’b1010_1011
171
3’d6
decimal 6
110
6’o42
octal 34
100010
8’hAB
hexadecimal 42
Unsized
00…

10. Bit Manipulations: Ex 1
assign y = {a[2:1], {3{b[0]}}, a[0], 6’b100_010};
// if y is a 12-bit signal, the above statement produces:
y = a[2] a[1] b[0] b[0] b[0] a[0]
// underscores (_) are used for formatting only to make it easier to read. Verilog ignores them.

11. Bit Manipulations: Ex 2 Verilog: Synthesis:
module mux2_8(input [7:0] d0, d1, input s, output [7:0] y); mux2 lsbmux(d0[3:0], d1[3:0], s, y[3:0]); mux2 msbmux(d0[7:4], d1[7:4], s, y[7:4]); endmodule
Verilog:
Synthesis:

12. Behavioral Statements
Statements that must be inside always statements:
if / else
case, casez
Reminder: Variables/signals assigned in an always statement must be declared as reg
(even if they’re not actually registered! More in a moment)

13. Comb. Logic using case Note the * module sevenseg(input [3:0] data,
output reg [6:0] segments);
case (data)
// abc_defg
0: segments = 7'b111_1110;
1: segments = 7'b011_0000;
2: segments = 7'b110_1101;
3: segments = 7'b111_1001;
4: segments = 7'b011_0011;
5: segments = 7'b101_1011;
6: segments = 7'b101_1111;
7: segments = 7'b111_0000;
8: segments = 7'b111_1111;
9: segments = 7'b111_1011;
default: segments = 7'b000_0000; // required
endcase
endmodule
Note the *

14. Synthesizing an Unwanted Latch?
Could happen!
Check the synthesizer output
In order for a case statement to imply combinational logic, all possible input combinations must be described by the HDL
Remember to use a default statement when necessary
May be good practice anyway
And all if statements w/ matching else

15. Combinational Logic using casez
module priority_casez(input [3:0] a,
output reg [3:0] y);
casez(a)
4'b1???: y = 4'b1000; // ? = don’t care
4'b01??: y = 4'b0100;
4'b001?: y = 4'b0010;
4'b0001: y = 4'b0001;
default: y = 4'b0000;
endcase
endmodule

16. Blocking vs. Nonblocking Assignments (review)
<= is a “nonblocking assignment”
Occurs simultaneously with others
= is a “blocking assignment”
Occurs in the order it appears in the file
// nonblocking assignments
module syncgood(input clk,
input d,
output reg q);
reg n1;
clk)
begin
n1 <= d; // nonblocking
q <= n1; // nonblocking
end
endmodule
// blocking assignments
module syncbad(input clk,
input d,
output reg q);
reg n1;
clk)
begin
n1 = d; // blocking
q = n1; // blocking
end
endmodule

17. Rules for Signal Assignment
Use clk) and nonblocking assignments (<=) to model synchronous sequential logic
(posedge clk)
q <= d; // nonblocking
Use continuous assignments (assign …) to model simple combinational logic.
assign y = a & b;
Use (*) and blocking assignments (=) to model more complicated combinational logic where the always statement is helpful.
Do not make assignments to the same signal in more than one always or continuous assignment statement

18. Next Topic
Finite State Machines
A basic sequential building block

19. Synchronous Sequential Logic Design
Registers contain the state of the system
The state changes at the clock edge, so system is synchronized to the clock
Rules:
Every circuit element is either a register or a combinational circuit
All registers receive the same clock signal (important!)
Every cyclic path contains at least one register
Two common synchronous sequential circuits
Finite State Machines (FSMs)
Pipelines

20. Finite State Machine (FSM)
Consists of:
State register that
Store the current state and
Loads the next state at clock edge
Combinational logic that
Computes the next state
Computes the outputs

21. Finite State Machines (FSMs)
Next state is determined by the current state and the inputs
Two types of finite state machines differ in the output logic:
Moore FSM: outputs depend only on the current state
Mealy FSM: outputs depend on the current state and the inputs

22. Moore and Mealy FSMs

23. FSM Example Traffic light controller
Traffic sensors: TA, TB (TRUE when there’s traffic)
Lights: LA, LB

24. FSM Black Box
Inputs: CLK, Reset, TA, TB
Outputs: LA, LB

25. Design Simple FSM When reset, LA is green and LB is red
As long as traffic on Academic (TA high), keep LA green
When TA goes low, sequence to traffic on Bravado
Follow same algorithm for Bravado
Let’s say clock is 5 secs. (time for yellow light)

26. States What sequence do the traffic lights follow?
Reset to State 0, LA is green and LB is red
Next (on board)?

27. State Transition Diagram
Moore FSM: outputs labeled in each state
States: Circles
Transitions: Arcs

28. State Transition Table

29. FSM Encoded State Transition Table

30. FSM Output Table

31. FSM Schematic: State Register

32. Next State Logic

33. Output Logic

34. FSM Timing Diagram

35. State Encoding Binary encoding: i.e., for four states, 00, 01, 10, 11
One-hot encoding
One state bit per state
Only one state bit is HIGH at once
I.e., for four states, 0001, 0010, 0100, 1000
Requires more flip-flops
Often next state and output logic is simpler
Synthesizer will often use one-hot (you can change)

36. Moore State Diagram
Inputs
State/Output

37. Mealy State Diagram
Output depends on input and state
Input/Output

38. State Table vs. Diagram Same information
Table is perhaps easier to fill in from description
Diagram is perhaps easier to understand
You can label states with English description

39. Design Procedure
Take problem description and refine it into a state table or diagram
Assign codes to the states
Derive Boolean equations and implement
Or, write Verilog and compile
See example next class
Designing with gates and FFs more involved because you have to derive input and output functions

40. Example – Sequence Recognizer
Circuit has input, X, and output, Z
Recognizes sequence 1101 on X
Specifically, if X has been 110 and next bit is 1, make Z high

41. How to Design States States remember past history
Clearly must remember we’ve seen 110 when next 1 comes along
Tell me one necessary state

42. Beginning State Start state: let’s call it A
If 1 appears, move to next state B
Input / Output

43. Second 1
New state, C
To reach C, must have seen 11

44. Next a 0 If 110 has been received, go to D
Next 1 will generate a 1 on output Z

45. What else? What happens to arrow on right? Must go to some state.
Where?

46. What Sequence? Here we have to interpret problem We’ve just seen 01
Is this beginning of new 1101?
Or do we need to start over w/ another 1?
Textbook: decides that it’s beginning (01…)

47. Cover every possibility
Well, must have every possibility out of every state
In this case, just two: X = 0 or 1
You fill in other cases

48. Fill in

49. Full Answer

50. State Minimization
When we make state diagram, do we need all those states?
Some may be redundant
State minimization procedures can be used
We won’t cover now

51. How to code FSM in Verilog
Case statement very useful here!
But first, let’s look at the parameter statement

52. Parameter – Just Shorthand
module seq_rec (CLK, RESET, X, Z);
input CLK, RESET, X;
output Z;
reg [1:0] state, next_state;
parameter A = 2'b00, B = 2'b01,
C = 2 'b10, D = 2'b11;
Notice that we’ve assigned codes to the states – more later

53. Next State always @(X or state) begin case (state) A: if (X == 1)
next_state <= B;
else
next_state <= A;
B: if(X) next_state <= C;else next_state <= A;
C: if(X) next_state <= C;else next_state <= D;
D: if(X) next_state <= B;else next_state <= A;
endcase
end
The last 3 cases do same thing.
Just sparse syntax.

54. On Reset or CLK always @(posedge CLK or posedge RESET) begin
if (RESET == 1)
state <= A;
else
state <= next_state;
end
Notice that state only gets updated
on posedge of clock (or on reset)

55. Output always @(X or state) begin case(state) A: Z <= 0;
B: Z <= 0;
C: Z <= 0;
D: Z <= X ? 1 : 0;
endcase
end

56. Comment on Code Could shorten Don’t need next_state, for example
Can just set state on clock
Don’t need three always clauses
Although it’s clearer to have combinational code be separate
Template helps synthesizer
Check to see whether your state machines were recognized

57. Work
Read
Might be good to look at Chapter 4 (Verilog only)

58. Today More Verilog Simple state machines Next Time
How to code them in Verilog
Next Time
Look at Moore equivalent of sequence recognizer
Delays and Timing

59. Read
Textbook Ch