1. Sequential Logic in Verilog
Taken From Digital Design and Computer Architecture
David Money Harris and Sarah L. Harris
Copyright © 2007 Elsevier

2. Sequential Logic
Verilog uses certain idioms to describe latches, flip-flops and FSMs
Other coding styles may simulate correctly but produce incorrect hardware
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3. Always Statement General Structure:
(sensitivity list)
statement;
Whenever the event in the sensitivity list occurs, the statement is executed
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4. D Flip-Flop
module flop(input clk,
input [3:0] d,
output reg [3:0] q);
(posedge clk)
q <= d; // pronounced “q gets d”
endmodule
Any signal assigned in an always statement must be declared reg. In this case q is declared as reg
Beware: A variable declared reg is not necessarily a registered output.
We will show examples of this later.
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5. Resettable D Flip-Flop
module flopr(input clk,
input reset,
input [3:0] d,
output reg [3:0] q);
// synchronous reset
(posedge clk)
if (reset) q <= 4'b0;
else q <= d;
endmodule
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6. Resettable D Flip-Flop
module flopr(input clk,
input reset,
input [3:0] d,
output reg [3:0] q);
// asynchronous reset
(posedge clk, posedge reset)
if (reset) q <= 4'b0;
else q <= d;
endmodule
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7. D Flip-Flop with Enable
module flopren(input clk,
input reset,
input en,
input [3:0] d,
output reg [3:0] q);
// asynchronous reset and enable
(posedge clk, posedge reset)
if (reset) q <= 4'b0;
else if (en) q <= d;
endmodule
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8. Latch
module latch(input clk,
input [3:0] d,
output reg [3:0] q);
(clk, d)
if (clk) q <= d;
endmodule
Warning: We won’t use latches in this course, but you might write code that inadvertently implies a latch. So if your synthesized hardware has latches in it, this indicates an error.
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9. Finite State Machines (FSMs)
Three blocks:
next state logic
state register
output logic
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10. FSM Example: Divide by 3 The double circle indicates the reset state
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11. FSM in Verilog: Divide by 3
module divideby3FSM (input clk, input reset, output q); reg [1:0] state, nextstate; parameter S0 = 2'b00; parameter S1 = 2'b01; parameter S2 = 2'b10; // state register (posedge clk, posedge reset) if (reset) state <= S0; else state <= nextstate; // next state logic (*) case (state) S0: nextstate = S1; S1: nextstate = S2; S2: nextstate = S0; default: nextstate = S0; endcase // output logic assign q = (state == S0); endmodule
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12. Moore vs. Mealy FSM
Alyssa P. Hacker has a snail that crawls down a paper tape with 1’s and 0’s on it. The snail smiles whenever the last four digits it has crawled over are Design Moore and Mealy FSMs of the snail’s brain.
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13. Snail Moore Machine
snailMoore.v
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14. JK Moore Machine Example
110 Detector designed with JK flip-flops
Design a machine with input A and output Y
Y should be one whenever the sequence has been detected on A on the last 3 consecutive rising clock edges or ticks.
Otherwise Y = 0
Timing diagram interpretation of word description
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15. State Diagram S A NS Y 00 (S0) 1 01 (S1) 10 (S2) 11 (S3)1
01 (S1)
10 (S2)
11 (S3)
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16. Transition Tables S1 S0 A S1+S0+ J1 K1 J0 K0 Y 0 0 (S0) 0 0 (S0) x 1
(S0) x 1
(S1)
0 1 (S1)
(S2)
1 0 (S2)
(S3)
1 1 (S3) J K Q+ Q 1 ~Q
Transition J K
0 => 0 x
0 => 1 1
1 => 0
1 => 1
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17. Verilog Implementation 1
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18. Verilog Implementation 2
JK FlipFlop in Verilog
testBench in Verilog
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