Clock & Control Card Status 31 March 2009 Martin Postranecky / Matt Warren

2 31 Mar. 2009Martin Postranecky / Matt Warren CALICE CCC – First Prototype

3 31 Mar. 2009Martin Postranecky / Matt Warren CALICE CCC – First Prototype

4 31 Mar. 2009Martin Postranecky / Matt Warren CCC - Custom Hardware CPLD Debug Header SMAs (vertical) Add-ons interface HDMIs LEMO (NIM) RS232

5 31 Mar. 2009Martin Postranecky / Matt Warren SW PCB Header 4x 4 4 8x LVDS on HDMI 8x LVDS on SMA 8x LVDS on HDMI LVDS on SMA LVTTL on Lemo NIM/TTL on Lemo LVDS on SMA 4x LVDS on SMA 4x NIM on Lemo 2x NIM on Lemo 2x LVTTL on Lemo LVDS on SMA NIM on Lemo o/c TTL on Lemo CLOCK ASYNC GEN (was BUSY) Controls (SYNCCMD, BUSY-IN etc) X-TAL MPX +PLL SW-2 5->1 SW-3 2->1 AUTO/ XTAL SW ~50 MHz 4 RS232 CCC - Overview Schematic CCC - Overview Schematic CPLD(XilinxCoolrunnerXCR3128XL-7) 8x LVDS on HDMI SPARE (DATA_D2L) LVTTL on Lemo DELAY clock DEBUG 4x 8way DIL ECL on 2pin Lemo

6 31 Mar. 2009Martin Postranecky / Matt Warren CCC - Logic and Interfaces Signal Inputs: CLOCKCLOCK –1x LVDS ( SMA DC ) –1x LVTTL DC ( Lemo ) –1x NIM / TTL ( Lemo ) AC/DC ASYNCASYNC –LVDS ( SMA ) DC –ECL ( 2 pin LEMO ) AC Controls ( SYNCCMD, BUSY etc. + more )Controls ( SYNCCMD, BUSY etc. + more ) –4x LVDS ( SMA ) –4x NIM / TTL ( Lemo ) AC/DC CPLD ( XCR3128XL-7 ) CPLD ( XCR3128XL-7 ) RS232 interface as a means of control RS232 interface as a means of control Many buffers, 0Ω resistors and solder links for better signal integrity, isolation and configuration Many buffers, 0Ω resistors and solder links for better signal integrity, isolation and configuration Signal Outputs: CLOCKCLOCK –2x LVTTL on Lemo –2x NIM on Lemo –2x LVDS on SMA –8x LVDS on DIL Header TRAINSYNCTRAINSYNC –LVTTL on Lemo GEN ( was Busy )GEN ( was Busy ) –LVDS on SMA –NIM on Lemo –O/C-TTL on Lemo Spare ( DATA_D2L )Spare ( DATA_D2L ) –LVTTL on Lemo HDMI I/O: x8 - LVDS AC/DC OUT: CLOCK CLOCK ASYNC ASYNC TRAINSYNC TRAINSYNCIN: GEN ( was BUSY ) GEN ( was BUSY ) SPARE( DATA_D2L ) SPARE( DATA_D2L )

7 31 Mar. 2009Martin Postranecky / Matt Warren Some Hardware Details Clock:Clock: –PLL/MUX - ICS /-150 ps jitter+/-150 ps jitter 45min/55max Duty Cycle45min/55max Duty Cycle Failover if external clock missing for 3 cycles.Failover if external clock missing for 3 cycles. –Local Osc. 100 MHz/2 = 50% duty-cycle 50MHz CPLD: Xilinx CoolRunner XPLA3 XCR3128XL-7CPLD: Xilinx CoolRunner XPLA3 XCR3128XL-7 –3.3V, low power –128 macrocells with 3,000 usable gates –5.5ns pin-to-pin logic delays Extra IO via IDC header.Extra IO via IDC header. Single 6U PCB with connectors at both edgesSingle 6U PCB with connectors at both edges Separate PSUSeparate PSU Clock Delay Option to CPLD – 64 x 0.5nsClock Delay Option to CPLD – 64 x 0.5ns –For signal de-skew ( CLOCK unaffected )

8 31 Mar. 2009Martin Postranecky / Matt Warren LVTTL Output Stand-alone Clock

9 31 Mar. 2009Martin Postranecky / Matt Warren LVTTL – Output Clock Jitter

10 31 Mar. 2009Martin Postranecky / Matt Warren CCC - Current Status 10x boards manufactured and assembled in x boards manufactured and assembled in x separate Power Supply units being assembled in x separate Power Supply units being assembled in x CCC undergoing testing in 2009 :10x CCC undergoing testing in 2009 : - 9x program OK - 9x program OK - number of irritating problems ( dry joints, missing connections, etc. ) - number of irritating problems ( dry joints, missing connections, etc. ) - 1x fails firmware programming ( suspect CPLD connections ) - 1x fails firmware programming ( suspect CPLD connections ) Aim to have 9x tested and working units in April Aim to have 9x tested and working units in April Basic ‘simple’ self-testing firmware now on CPLD Basic ‘simple’ self-testing firmware now on CPLD ‘Run’ firmware is in development : COMING SOON ! ‘Run’ firmware is in development : COMING SOON ! Serial Interface details on Twiki Serial Interface details on Twiki Hardware Manual draft : Hardware Manual draft : TWIKI pages : TWIKI pages :

11 31 Mar. 2009Martin Postranecky / Matt Warren Spare slides…. FEW PREVIOUSLY SHOWN / SPARE SLIDES

12 31 Mar. 2009Martin Postranecky / Matt Warren DAQ PC CALICE - DAQ architecture CALICE - DAQ architecture Detector Unit: ASICs DIF : Detector InterFace connects Generic DAQ and services LDA : Link / Data Aggregator – fan-out / in DIFs and drives link to ODR LDA ODR CCC Detector Unit DIF ODR : Off Detector Receiver – PC interface for system. interface for system. CCC : Clock & Control Card: Fanout to ODRs ( or LDAs ) to ODRs ( or LDAs ) CONTROL PC: DOOCS GUI ( run control ) control ) Storage Control PC (DOOCS) DAQ PC ODR Detector Unit DIF Detector Unit DIF Detector Unit DIF

13 31 Mar. 2009Martin Postranecky / Matt Warren CCC - Timing Overview CCC - Timing Overview C+C provides a fast clock ( CLOCK )C+C provides a fast clock ( CLOCK ) – Assumed to be ~50 MHz, local or machine – Stand-alone clock can be 50 or 100 MHz CCC does NOT support varied delays on individual outputsCCC does NOT support varied delays on individual outputs CCC card can adjust timing of synchro-signals wrt. CLOCKCCC card can adjust timing of synchro-signals wrt. CLOCK

14 31 Mar. 2009Martin Postranecky / Matt Warren CCC - Link Interface CCC can connects to LDA, DIF and ODR using the ‘standard’ HDMI cabling and connectors and pinout ( Clink )CCC can connects to LDA, DIF and ODR using the ‘standard’ HDMI cabling and connectors and pinout ( Clink ) – But only a subset of the signals/functions used – CCC can be used as a pseudo-LDA for stand-alone DIF testing A distinction is made between fast and fixed latency signals.A distinction is made between fast and fixed latency signals. – Fast signaling is asynchronous and uses a dedicated line to transfer a pulse. No attempt is made to encode data pulse. No attempt is made to encode data – Fixed-latency signaling will not arrive fast, but will arrive a known latency after reception by CCC latency after reception by CCC HDMI Signals CLink SignalDirectionFunctionType CLOCK_L2D LDA → DIF Distributed DIF ClockSTP DATA_L2D LDA → DIF Data to DIF (mainly configuration)STP DATA_D2L DIF → LDA Data from DIF (mainly events)STP ASYNC_L2D LDA → DIF Asynchronous triggerUTP* GEN_D2L DIF → LDA General useSTP * Twisted pair not guaranteed by HDMI specification but seen in commercial cables

15 31 Mar. 2009Martin Postranecky / Matt Warren CCC - Link Signals CCC - Link Signals CLOCKCLOCK –Machine clock ( MHz) TRAINSYNC_OUTTRAINSYNC_OUT –Synchronisation of all the front-end slow clocks –An external signal will be synchronized to the clock and transmitted as a single clock-period wide pulse to the LDA –To allow communicating with a stand-alone DIF, the CCC board will can be configured to send the LDA 8b/10b serialised command for train-sync ASYNC_OUTASYNC_OUT –Transfer asynchronous triggers as fast as possible GEN_INGEN_IN –General purpose signal for use in communicating with the CCC ( and therefore run control ) system. A hardware OR of these signals is available on the CCC CCC HDMI Signals CLink SignalCCC SignalFunction CLOCK_L2DCLOCK_OUTClock DATA_L2DTRAINSYNC_OUTTrainsync signal output DATA_D2LUnused ASYNC_L2DASYNC_OUTAsynchronous signal GEN_D2LGEN_INGeneral purpose