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DAQ PC CALICE DAQ architecture Detector Unit : ASICs DIF : Detector InterFace connects Generic DAQ and services LDA : Link / Data Aggregator – fanout /

Published byClare Johnson Modified over 8 years ago

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Presentation on theme: "DAQ PC CALICE DAQ architecture Detector Unit : ASICs DIF : Detector InterFace connects Generic DAQ and services LDA : Link / Data Aggregator – fanout /"— Presentation transcript:

1 DAQ PC CALICE DAQ architecture Detector Unit : ASICs DIF : Detector InterFace connects Generic DAQ and services LDA : Link / Data Aggregator – fanout / in DIFs and drives link to ODR LDA ODR CCC Detector Unit DIF ODR : Off Detector Receiver - - PC interface for system CCC : Clock & Control Card: Fanout to ODRs ( or LDAs ) CONTROL PC : DOOCS GUI ( run-control ) Storage Control PC (DOOCS) DAQ PC ODR Detector Unit DIF Detector Unit DIF Detector Unit DIF

2 CCC HDMI Signals CLink SignalCCC SignalFunction CLOCK_L2DCLOCK_OUTClock DATA_L2DTRAINSYNC_OUTTrainsync signal output DATA_D2LUnused ASYNC_L2DASYNC_OUTAsynchronous signal GEN_D2LGEN_INGeneral purpose

3 SW PCB Header 4x 4 4 8x LVDS on HDMI 8x LVDS on SMA 8x LVDS on HDMI LVDS on SMA LVTTL on Lemo NIM/TTL on Lemo LVDS on SMA 4x LVDS on SMA 4x NIM on Lemo 2x NIM on Lemo 2x LVTTL on Lemo LVDS on SMA NIM on Lemo o/c TTL on Lemo CLOCK ASYNC GEN (was BUSY) Controls (SYNCCMD, BUSY-IN etc) X-TAL MPX +PLL SW-2 5->1 SW-3 2->1 AUTO/ XTAL SW ~50 MHz 4 RS232 CPLD(XilinxCoolrunnerXCR3128XL-7) 8x LVDS on HDMI SPARE (DATA_D2L) LVTTL on Lemo DELAY clock DEBUG 4x 8way DIL ECL on 2pin Lemo

4 CPLD Debug Header SMAs (vertical) Add-ons interface HDMIs LEMO (NIM) RS232

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