CPU Structure CPU must: Fetch instructions: The processor reads an instruction from memory. Interpret instructions: The instruction is decoded to determine what action is required. Fetch data: Reading data from memory or I/O. Process data: Performing required arithmetic or logical operations on data. Write data: writing data to memory or I/O. 22

Registers CPU must have some working space (temporary storage) Called registers. Number and function vary between processor designs One of the major design decisions Top level of memory hierarchy Categories: General Purpose Data Address Condition Codes 23

General Purpose Registers (1) May be true general purpose May be restricted May be used for data or addressing Data Accumulator Addressing Segment 25

General Purpose Registers (2) Make them general purpose Increase flexibility and programmer options Increase instruction size & complexity Make them specialized Smaller (faster) instructions Less flexibility Between 8 – 32 registers. Fewer = more memory references More does not reduce memory references 26

How big? Large enough to hold full address Large enough to hold full word Often possible to combine two data registers C programming double int a; long int a; 28

Condition Code Registers Sets of individual bits e.g. result of last operation was zero Can be read (implicitly) by programs e.g. Jump if zero Can not (usually) be set by programs 29

Control & Status Registers Program Counter: contains address of an instruction to be fetched. Instruction Decoding Register: contains the instruction most recently fetched. Memory Address Register: contains the address of a location in memory. Memory Buffer Register: contains a word of data to be written to memory or the word most recently read. 30

What is an “Architecture”? When we refer to “Architecture,” we often use it as an abbreviation for an instruction set architecture (ISA). The ISA is the interface between hardware and software. The architecture is a specification for what the processor will do, and how the software must communicate to the processor. Note that the “architecture” states only what will be done, but not how.

RISC The design goals and principles behind reduced instruction set computers (RISC) are: Smaller is faster Simplicity favors regularity Make the common case fast Regularity will basically apply to instruction sizes and instruction formats. RISC architectures have a fewer number of simple instructions than complex instruction set computer (CISC) architectures. Access to memory using Load and Store command only.

MIPS MIPS is a common RISC ISA. MIPS processors are in extensive use by NEC, Nintendo, Cisco, SGI, Sony, etc. MIPS has 32 integer registers. It uses only a limited number of addressing modes. MIPS has a fairly regular instruction encoding. All instructions are 32 bits long (4 bytes), and there are only three instruction formats

MIPS Arithmetic Instructions MIPS arithmetic instructions have three operands: add a, b, c This instruction takes the sum of registers b and c and puts the answer into register a. It is equivalent to the C code: a = b + c; What if we want to code the following? a = b + c + d; We need to do it in two steps: add a, a, d Note that multiple operands may refer to the same register

MIPS Registers and Memory In MIPS, the operands must be registers. 32 registers are provided each register stores a 32-bit value. The compilers associate variables with registers registers are referred to by names such as $s0 and $t1 we use the “s” registers for values that correspond to variables in our programs, and we use the “t” registers for temporary values (more on this later)

MIPS Registers and Memory 2 For example, consider this example from the text: f = (g + h) - (i + j); We choose registers to store the values of our variables: f in $s0, g in $s1, h in $s2, i in $s3, and j in $s4. We’ll also need to temporary values, which we will store in $t0 and $t1. The MIPS code: add $t0, $s1, $s2 add $t1, $s3, $s4 sub $s0, $t0, $t1

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