1. COMS 361 Computer Organization
Title: Instructions
Date: 9/14/2004
Lecture Number: 6

2. Announcements
Homework 3
Due 9/21/04

3. Review
MIPS, MOPS, FLOPS
SPEC Benchmarks

4. Outline Instructions MIPS arithmetic instruction format
Design principles
Registers
Memory organization
MIPS load and store instructions and format
Addressing
MIPS branch instructions and format

5. Instructions Instructions: Instruction set:
Words of a computers language
More primitive than higher level languages
No sophisticated control flow
Essentially a goto is the only mechanism to alter sequential program execution
Very restrictive
MIPS Arithmetic Instructions
Instruction set:
Vocabulary of the language

6. Instructions MIPS instruction set architecture
Similar to other architectures developed since the 1980's
Used by NEC, Nintendo, Silicon Graphics, Sony
Design goals for all ISA’s
Maximize performance
Minimize cost
Reduce design time
Machine languages for different machines are similar as common tasks must be performed

7. MIPS arithmetic All arithmetic instructions have 3 operands Example:
Fixed operand order (destination first)
Example:
C/C++ code: a = b + c
MIPS code: add $s0, $s1, $s2
means $s0 <= $s1 + $S2
Rigid arithmetic instruction format
MIPS arithmetic instruction
Performs one operation
Has exactly three variables
Destination (a)
One source (b)
The other source (c)

8. MIPS arithmetic
Natural: add two numbers and put the result somewhere else
Less flexibility => simpler hardware
C/C++ code: a = b + c + d
MIPS code: add $s0, $s1, $s2
add $s0, $s0, $s3
To add three numbers requires two MIPS instructions
There can be only one instruction per line
The regularity of arithmetic instructions make implementation simpler than hardware for a variable number of operands

9. Design Principle 1 Simplicity favors regularity
Regularity complicates some things
C/C++ code: a = b + c + d;
e = f - a;
MIPS code: add $t0, $s1, $s2 add $s0, $t0, $s3 sub $s4, $s5, $s0

10. MIPS arithmetic Operands must be registers in the MIPS ISA
Registers are fast memory units on the processor
MIPS has 32 registers, each containing 32 bits
Assembler names for some of the registers
$zero: constant 0
$at: reserved for the assembler
$v0 - $v1: function results
$a0 - $a3: function arguments
$t0 - $t9: temporary (not preserved)
$s0 - $s7: temporary (preserved)
$k0 - $k1: reserved for the OS kernel
$gp, $sp, $fp, $ra: special purpose registers

11. Design Principle 2 Smaller is faster
Compiler associates program variables with registers
What about programs with lots of variables?
More variables than the number of registers
Spilled to memory
Processor
I/O
Control
Datapath
Memory
Input
Output

12. Registers and Memory Data Transfer Instructions
MIPS provides a mechanism to transfer data between memory and registers
Must contain a memory address
More on this later

13. Memory Organization
Viewed as a large, single-dimension array, with an address
A memory address is an index into the array
"Byte addressing" means that the index points to a byte of memory 1 2 3 4 5 6
...
8 bits of data

14. Memory Organization Bytes are nice, but bigger is better (right?)
A byte holds a small amount of information
Group bytes into a word
For MIPS, a word is 32 bits or 4 bytes 4 8 12
32 bits of data
Each registers holds 32 bits of data

15. Memory Organization 232 bytes with byte addresses from 0 to 232-1
230 words with byte addresses 0, 4, 8,
Words are aligned (alignment restriction)
Sequential word addresses differ by 4
What are the least two significant bits of each word address?

16. Memory Organization Two choices for the order the bytes fill a word
Leftmost byte in a word
Big-end: Big Endian
MIPS
Rightmost byte in a word
Little-end: Little Endian
Intel
byte 0 byte 1 byte 2 byte 3 4
byte 4 byte 5 byte 6 byte 7
byte 3 byte 2 byte 1 byte 0 4
byte 7 byte 6 byte 5 byte 4

17. Data Transfer Instructions
Transfer data between registers and memory
Load and store instructions
Only way for MIPS to read/save data from/in memory
Must specify the address in memory of the word
load
Move data from memory into a register
store
Move data from a register into memory

18. Data Transfer Instructions
Example
C/C++ code: A[8] = h + A[8];
Add the contents of a register to the contents of a memory location
MIPS: operands must be registers
load operands into registers
perform the add
store sum

19. Data Transfer Instructions
Example
C/C++ code: A[8] = h + A[8];
MIPS code: lw $t0, 32($s3) add $t0, $s2, $t0 sw $t0, 32($s3)
One simple high-level language statement results in three MIPS instructions

20. Data Transfer Instructions
base address
The address of the first element of the array A
Stored in $s3 called the base register
offset
Amount added to the base register to index a specific element in the array
Add an amount to access the 8th array element
MIPS is byte addressed and words are 4 bytes
add 32 to the base address of the array

21. Data Transfer Instructions
Store word (sw) has destination (memory address) last
Store the word in a register to a memory location
Arithmetic operands are registers, not memory!

22. So far MIPS Loading words but addressing bytes
Arithmetic on registers only
Instruction Meaning
add $s1, $s2, $s3 $s1 = $s2 + $s3
sub $s1, $s2, $s3 $s1 = $s2 – $s3
lw $s1, 100($s2) $s1 = Memory[$s2+100]
sw $s1, 100($s2) Memory[$s2+100] = $s1