Presentation on theme: "CSCI 4717/5717 Computer Architecture"— Presentation transcript:
1 CSCI 4717/5717 Computer Architecture Topic: CPU RegistersReading: Stallings, Sections 10.3, 10.4, 12.1, and 12.2
2 CPU Internal Design Issues CPU design and operating system design are closely linkedCompiler design also has heavy dependence on CPU designThe primary CPU design characteristics as seen by the O/S and the compiler are:Instruction setRegisters (number and purpose)
3 How Many Instructions are Needed? Instruction sets have been designed withSmall numbers of instructionsHundreds of instructionsTrend today is to use “enough” to get the job done well (more on this in the RISC/CISC discussions to come)
4 How Many Instructions are Needed? Until the 1980s, the trend was to construct more and more complex instruction sets containing hundreds of instructions and variationsIntent was to provide mechanisms to bridge the semantic gap, the difference in high and low level functioning of the computer
5 Bridging the Semantic Gap Reconcile the views of the HLL programmer and the assembly level programmerProvide a diverse set of instructions in an attempt to match the programming style of HLLPermit the compiler to “bridge the gap” with a single instruction rather than synthesizing a series of instructionsDid not always have the desired impact
6 Addresses in an Instruction In a typical arithmetic or logical instruction, 3 references are required2 operandsa resultThese addresses can be explicitly given or implied by the instruction
7 3 address instructionsBoth operands and the destination for the result are explicitly contained in the instruction wordExample: X = Y + ZWith memory speeds (due to caching) approaching the speed of the processor, this gives a high degree of flexibility to the compilerTo avoid the hassles of keeping items in the register set, use memory as one large set of registersThis format is rarely used due to the length of addresses themselves and the resulting length of the instruction words
8 2 address instructionsOne of the addresses is used to specify both an operand and the result locationExample: X = X + YVery common in instruction setsSupported by heavy use in HLL of operations such as A += B or C <<=3; ADD A,B ;A = A + B SHL C,3 ;Shift C left 3 bits
9 1 address instructionsWhen only a single reference is allowed in an instruction, another reference must be included as part of the instructionTraditional accumulator-based operationsExample: Acc = Acc + XFor an instruction such as A += B, code must first load A into an accumulator, then add B. LOAD A ADD B
10 0 address instructionsAll addresses are implied, as in register-based operations – e.g., TBA (transfer register B to A)Zero address instructions imply stack-based operationsAll operations are based on the use of a stack in memory to store operandsInteract with the stack (simulate the loading of registers) using push and pop operations
11 Trade off Resulting from Fewer Addresses Fewer addresses in the instruction results in:More primitive instructions – less complex CPUInstructions with shorter length – fit more into memoryMore total instructions in a programLonger, more complex programsFaster fetch/execution of instructions – fewer loops in operand fetches and storesBut does it create longer execution times?
12 Example: 3 Addresses Y = (A-B) / (C+D*E) SUB Y,A,B MUL T,D,E ADD T,T,C DIV Y,Y,T
13 Example: 2 address Y = (A-B) / (C+D*E) MOV Y,A SUB Y,B MOV T,D MUL T,E ADD T,CDIV Y,T
14 Example: 1 address Y = (A-B) / (C+D*E) LOAD D MUL E ADD C STORE Y LOAD ASUB BDIV Y
15 Example: 0 address – Convert to postfix (reverse Polish) notation: PUSH APUSH BSUBPUSH CPUSH DPUSH EMULADDDIVPOP YY = (A-B) / (C+D*E) becomes Y = AB–CDE*+/This is "Postfix" or "Reverse Polish Form" from tree searching.
16 Instruction Set Design Decisions Operation repertoireHow many ops?What can they do?How complex are they?Data types – various types of operations and how they are performedInstruction formatsLength of op code fieldNumber of addresses
17 CPU Internal Design Issues From our discussion of the architecture of the computer, we've put some requirements on the CPU.CPU fetches instructions from memoryCPU interprets instructions to determine action that is requiredCPU fetches data that may be required for execution (could come from memory or I/O)CPU processes data with arithmetic, logic, or some movement of dataCPU writes data (results) to memory or I/O
18 CPU Internal Structure Design decisions here affect instruction set design
19 CPU Internal Structure – ALU, Internal CPU Bus, and Control Unit Arithmetic Logic UnitStatus flagsShifterComplementerArithmetic logicBoolean logicInternal CPU bus to pass data back and forth between components of the CPUControl unit – managing operation of all CPU components
20 CPU Internal Structure – Registers CPU must have some working space (temporary storage) to remember thingsdata being operated onpointers to memory (code, stack, data)machine code of current instructionNumber and function vary between processor designsThis is one of the major design decisionsAbsolute top level of memory hierarchy
21 CPU Internal Structure – Registers (continued) Two types of registers:User-visible registers -- allow for operations with minimal interaction with main memory (programmer acts like cache controller for registers)Control and Status Registers -- with correct privileges, can be set by programmer. Lesser privileges may provide read-only capability.
22 User Visible Registers Represent complete user-oriented view of processor. Therefore, storing and later reloading of all user-visible registers effectively resets processor back to stored state as if nothing ever happened.Accessed with assembly language instructionsGeneral purpose – no assigned purposeData – may be restricted to floating point or integerAddress/pointer – may be restricted to code, stack, data, index, or segmentCondition codes/flags
23 Register Design Issues The range of design decisions goes from…Make all registers general purposeIncrease flexibility and programmer optionsIncrease instruction size & complexityMake all registers specializedSmaller more specialized (faster) instructionsLess flexibility
24 Register Design Issues (continued) How many general purpose registers?Number affects instruction set design => more registers means more operand identifier bitsBetween 8 – 32Remember that the registers are at the top of the hierarchy faster than cacheThe fewer GP registers, the more memory referencesMore registers do not necessarily reduce memory references, but they do take up processor real estateRISC needs are different and will be discussed later
25 Register Design Issues (continued) How big do we make the registers?Address – large enough to hold full addressData – large enough to hold full wordOften possible to combine two data registers (e.g., AH + AL = AX) This is useful with operations such as multiply.Example: Do we link the design of registers to a standard, e.g., C programmingdouble int a;long int a;
26 Condition Code Registers (Flags) Sets of individual bits each with a unique purpose (e.g. result of last operation was zero)Branch opcodes can read flag values to determine outcome of last operation (e.g., branch if result was positive)Most are automatically set as a result of an operationSome processors allow user to set or clear them explicitlyCollected into group and referred to as a single register (CCR). Makes storing to stack easier.
27 Control & Status Registers Types of control & status registersRegisters for movement of data between CPU and memoryProgram Counter (PC)Instruction Register (IR)Memory Address Register (MAR)Memory Buffer Register (MBR)Optional buffers used to exchange data between ALU, MBR, and user-visible registersProgram Status Word (PSW)Address pointers used for controlBuilt-in processor I/O control & status registers
28 Control & Status Registers (continued) Program Counter (PC)Automatically incremented to next instruction as part of operation of current instructionCan also be changed as result of jump instructionInstruction Register (IR)Most recently fetched instructionsWhere instruction decoder examines opcode to figure out what to do next
29 Control & Status Registers (continued) Memory Address Register (MAR)Memory address of current memory location to fetchCould be instruction or dataMemory Buffer Register (MBR)Last word read from memory (instruction or data)Word to be stored to memory
30 Control & Status Registers (continued) Program Status Word (PSW) – May be exactly the same thing as user-visible condition code registerA set of bits which include condition codesSign of last resultZeroCarryEqualOverflowInterrupt enable/disableSupervisorExamples: Intel ring zero, kernel mode, enable exceptions, direction of string operationsAllows privileged instructions to executeUsed by operating systemTypically not available to user programs
31 Control & Status Registers (continued) Address pointers used for controlInterrupt vectorsSystem stack pointerPage table pointer for hardware supported virtual memoryChip select controlsOn processor I/OStatus and control to operate the I/OE.g., serial ports -- bps rate, interrupt enables, buffer registers, etc.