ASP-DAC 2015 SC/OC Meeting TPC Report for ASP-DAC 2016 TingTing Hwang, National Tsing Hua Univ. TPC Chair for ASP-DAC 2016 tingting@cs.nthu.edu.tw

Outlines Call-for-paper and plan for sub-committee Important dates

2015 Call for Paper 1. System-Level Modeling and Design Methodologies 2. Embedded System Architectures and Design 3. On-chip Communication and Networks-on-Chips 4. System-on-Chip Architectures and Design 5. Device/Circuit-Level Modeling, Simulation and Verification 6. Logic/Behavioral/High-Level Synthesis and Optimizations 7. Analog, RF and Mixed Signals 8. System-Level Power and Thermal Management 9. Device/Circuit/Gate-Level Low Power Design 10. Embedded Software 11. Physical Design 12. Timing and Signal/Power Integrity 13. Design for Manufacturability and Reliability 14. Test and Design for Testability 15. Security and Fault-Tolerant Systems 16. Emerging Technologies 17. Emerging Applications I 18. Emerging Applications II

2016 Call for Paper 1. System-Level Modeling and Design Methodologies 2. Embedded System Architectures and Design 3. On-chip Communication and Networks-on-Chips 4. Embedded Software 5. Device/Circuit-Level Modeling, Simulation and Verification 6. Analog, RF and Mixed Signals 7. System-Level Power and Thermal Management 8. Device/Circuit/Gate-Level Low Power Design 9. Logic/Behavioral/High-Level Synthesis and Optimizations 10. Physical Design 11. Design for Manufacturability and Reliability 12. Timing and Signal/Power Integrity 13. Test and Design for Testability 14. Security and Fault-Tolerant Systems 15. Emerging Technologies 16. Emerging Applications

Comparisons of 2015/16 2016 CFP 2015 CFP 1. System-Level Modeling and Design Methodologies 2. Embedded System Architectures and Design 3. On-chip Communication and Networks-on-Chips 4. Embedded Software 5. Device/Circuit-Level Modeling, Simulation and Verification 6. Analog, RF and Mixed Signals 7. System-Level Power and Thermal Management 8. Device/Circuit/Gate-Level Low Power Design 9. Logic/Behavioral/High-Level Synthesis and Optimizations 10. Physical Design 11. Design for Manufacturability and Reliability 12. Timing and Signal/Power Integrity 13. Test and Design for Testability 14. Security and Fault-Tolerant Systems 15. Emerging Technologies 16. Emerging Applications 2015 CFP 1. System-Level Modeling and Design Methodologies 2. Embedded System Architectures and Design 3. On-chip Communication and Networks-on-Chips 4. System-on-Chip Architectures and Design 5. Device/Circuit-Level Modeling, Simulation and Verification 6. Logic/Behavioral/High-Level Synthesis and Optimizations 7. Analog, RF and Mixed Signals 8. System-Level Power and Thermal Management 9. Device/Circuit/Gate-Level Low Power Design 10. Embedded Software 11. Physical Design 12. Timing and Signal/Power Integrity 13. Design for Manufacturability and Reliability 14. Test and Design for Testability 15. Security and Fault-Tolerant Systems 16. Emerging Technologies 17. Emerging Applications I 18. Emerging Applications II 顏色表示merge，其餘不變，只微調順序

Topic (subcommittee) Name 2016 Subcommittee Plan Topic ID Topic (subcommittee) Name TPC Size (2015) 1 System-Level Modeling and Design Methodologies 7(7) 2 Embedded System Architectures and Design 11(7+4) 3 On-chip Communication and Networks-on-Chips 6 (6) 4 Embedded Software 5 Device/Circuit-Level Modeling, Simulation and Verification 6(6) 6 Analog, RF and Mixed Signals 5(5) 7 System-Level Power and Thermal Management 8 Device/Circuit/Gate-Level Low Power Design 5 (5) 9 Logic/Behavioral/High-Level Synthesis and Optimizations 10 Physical Design 11 Design for Manufacturability and Reliability 12 Timing and Signal/Power Integrity 4 (4) 13 Test and Design for Testability 14 Security and Fault-Tolerant Systems 15 Emerging Technologies 16 Emerging Applications 8 (4+4) Total 100 (100) 括號表是2015的實際數字

Important Dates Deadline for submission: 5 PM AOE (Anywhere on Earth), July 8 (Wed), 2015 TPC meeting: Aug. 31 (Mon) 2015 held in Hsin-Chu, Taiwan Formal notification of acceptance: Sep. 14 (Mon), 2015 Acceptance/rejection results posted on website: Sep. 3, 2015 DATE paper deadline: Sep. 13 (Sun), 2015 Deadline for final version: 5 PM AOE, Nov. 9 (Mon), 2015

Track Members' COI Track Chairs may submit their papers to their track, but the papers are handled by TPC Chair TPC members whose papers are accepted in their tracks should step out during the best paper nomination discussion

Thank you