1. EE 201C Modeling of VLSI Circuits and Systems Chapter 1 Introduction
Instructor: Lei He

2. Instructor Info
Phone:
Office: Boelter Hall 6731D
Office hours:
Tus 2-3pm
Thur 4-5pm
or by appointment
The best way to reach me:
with EE201 in subject line
I will first briefly give the background and overview of my dissertation, then cover more details for an important component of the dissertation: the
LR-base STIS optimization. Here LR refers to local refinement, and STIS refers to simultaneous transistor and interconnect sizing. Finally, we draw conclusions and discuss future works.

3. VLSI Design and Verification Cycle
System Specification
Functional Design and Verification
X=(AB*CD)+(A+D)+(A(B+C))
Y=(A(B+C))+AC+D+A(BC+D))
Logic Design and Verification
Circuit Design and Verification
Verification techniques
Formal verification
Logic/circuit simulation
Functional and logic emulation

4. VLSI Design and Verification Cycle (cont.)
Physical Design and Verification
Fabrication and Testing
Packaging
Layout verification
LVS, DRC, ERC
Timing, SI, PI, DFM (applied to circuit design as well)
Modeling and simulation is a core component for design and verification considering timing/SI/PI/DFM

5. CAD Courses at UCLA EE dept. CS dept.
EE201A Fundamental to CAD (each fall)
Basics to all aspects of CAD
More on combinatorial optimization
EE201C this course (each Spring)
Modeling and simulation of timing, signal/power integrity, and manufacturability for digital and mixed-signal circuits
Co-development of numerical modeling and optimization
EE209 Better Interface between design and manufacturing (taught by Puneet Gupta each winter)
CS dept.
CS258F Physical design of VLSI circuits
CS258G Logic synthesis of VLSI circuits
CS259 High Level Synthesis
I will first briefly give the background and overview of my dissertation, then cover more details for an important component of the dissertation: the
LR-base STIS optimization. Here LR refers to local refinement, and STIS refers to simultaneous transistor and interconnect sizing. Finally, we draw conclusions and discuss future works.

6. 201C Course Outline and Schedule
Interconnect and timing modeling (3 weeks)
Interconnect extraction
Delay modeling and model order reduction
Project 1 (model order reduction in Matlab)
On-chip timing and integrity (4 weeks)
Static timing and noise analysis for logic and on-chip interconnects
Process variation, stochastic timing, power and noise analysis
Stochastic power and thermal integrity
Project 2 (stochastic modeling in Matlab)
Beyond-die signal and power integrity (3 weeks)
Chip-package co-design with signal and power integrity
Noise analysis for high-speed signaling and other analog components
Final project: Independent study of selected topics
Plus, in-class or video presentations by students

7. Programming Projects Project 1: Matlab coding of PRIMA
model order reduction method
Majority of program is given
Project 2: Matlab coding of stochastic model selected from
Max operation for timing
Leakage power due to processing variation
Eye open for high-speed signaling
Again, majority of codes is given

8. Student Presentation One presentation a week by students
On-campus program (two students a group)
Video may be used if there is not enough time slots
Online MS program (one presentation per student via video)
Papers and initial slides draft provided
Final slides and references uploaded to wiki by students

9. Final Project Independent study of selected topic
Could be a single student or a team of students
Topic can be decided anytime, but no later than week 8
One or two “seed” papers provided
Develop a report based on literature search or other forms of independent study
Up to 12 page report using ACM style
Deliver a 30 minute presentation during the finals week, like a conference talk (video for online program)
Again, reports, references, and video uploaded to wiki

10. References for this Course
Web sites
Selected papers leading journals and conferences
Tan and He, “Advanced Model Order Reduction Techniques for VLSI Designs”, Cambridge University Press, pp 1-217, 2006
H. Bakoglu, Circuits, Interconnects, and Packaging for VLSI, Addison Wesley
I will first briefly give the background and overview of my dissertation, then cover more details for an important component of the dissertation: the
LR-base STIS optimization. Here LR refers to local refinement, and STIS refers to simultaneous transistor and interconnect sizing. Finally, we draw conclusions and discuss future works.

11. Related VLSI CAD Conferences
ACM IEEE Design Automation Conference (DAC)
(San Diego, Young student program)
International Conference on Computer Aided Design(ICCAD)
Design, Automation and Test in Europe (DATE)
Asia and South Pacific Design Automation Conference (ASP-DAC)
International symposium on physical design (ISPD)
International symposium on low power electronics and design
International symposium on field programmable gate array
IEEE International Symposium on Circuits and Systems (ISCAS)

12. Related VLSI CAD Journals
IEEE Transactions on CAD of Circuits and systems (TCAD)
IEEE Trans. on VLSI Systems (TVLSI)
ACM Trans. on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Circuits and Systems (TCAS)
IEEE Trans. on Computer

13. Grading Policy Two Matlab Projects 50% Course presentation 10%
Final project 40%
A  score > 85
I will first briefly give the background and overview of my dissertation, then cover more details for an important component of the dissertation: the
LR-base STIS optimization. Here LR refers to local refinement, and STIS refers to simultaneous transistor and interconnect sizing. Finally, we draw conclusions and discuss future works.

14. Who should take this course
For students who are motivated to
Learn SI, power/thermal, DFM for advanced designs
Understand CAD better
Become a CAD professional
I will first briefly give the background and overview of my dissertation, then cover more details for an important component of the dissertation: the
LR-base STIS optimization. Here LR refers to local refinement, and STIS refers to simultaneous transistor and interconnect sizing. Finally, we draw conclusions and discuss future works.