SEQUOIA Physical & Timing Verification of Subwavelength-Scale Designs using Physical Simulation Robert Pack ( formerly of Cadence Berkeley Labs) Valery Axelrad, Andrei Shibkov, Victor Boksha ( Sequoia Design Integration, Inc.) Judy Huckabay, Rachid Salik, Wolf Staud (Cadence Design Systems, Inc.) Ruoping Wang, Warren Grobman ( Motorola Inc. )

SEQUOIA Outline Introduction Introduction Problem Statement Problem Statement OPE Impact on Device Performance OPE Impact on Device Performance OPE and RET effects OPE and RET effects Timing Analysis Timing Analysis Multi-partioning of critical devices Multi-partioning of critical devices Summary Summary

SEQUOIA Introduction DPI closure is key for successful <130nm designs DPI closure is key for successful <130nm designs Current state-of-art EDA tools insufficient insufficient in predicting performance insufficient in predicting yield/reliability Timing, SI, Race Conditions, Power… +/- %100 These factors are responsible for costly fabrication yield re-spins – >%30 !. Failure Costs are high! Residual design-to-silicon distortions Design and verification must account for increased process and device physics entanglement Novel verification approach unique new adjunct to DFM and MSO flows

SEQUOIA Problem statement Excessive Re-spins Excessive Re-spins Large % of flaws Large % of flaws due to SI and Power due to SI and Power Parametric and Catastrophic Yield Loss Parametric and Catastrophic Yield Loss Feature Limited Feature Limited Reliability Issue Reliability Issue Proximity Effects Proximity Effects Device Device LITHOGRAHIC LITHOGRAHIC Mitigation: OPC/PSM Mitigation: OPC/PSM Design Tools lack ability Design Tools lack ability to capture complex physical effects Source: Kibarian/PDF Solutions & Collet

SEQUOIA Silicon Verification must be performed before committing a SubWavelength design to silicon. Design PASS ! Layout - DRC Layout - LVS Layout - Timing Physical Verification Layout Silicon - DRC X Silicon - LVS X Silicon - Timing X Silicon Level Verification Compares silicon to layout FAIL!

SEQUOIA Specific Problem: Silicon-Level Verification Industry focusing on Interconnects - OPE Impact on Device Performance

SEQUOIA Verification of Process Proximity Effects - through physical simulation OPE distortion affects transistor performance and matching OPE distortion affects parasitics extraction accuracy OPE is the major deterministic source of device variability OPE is the major deterministic source of device variability electrical impact of image quality electrical impact of image quality gate length variation gate length variation line end pullback line end pullback Complicates performance estimation / bin sort yield

SEQUOIA OPE is the major deterministic source of device variability OPE impacts device performance characteristics Vth Idsat Ioff Power (leakage) Yield/Reliability

SEQUOIA Additional Complexity

SEQUOIA Experimental Simulation Conditions 248nm 248nm NA=0.7 NA=0.7 Source: Source: Binary and OPC Binary and OPC Pillbox; Sigma=0.6 Pillbox; Sigma=0.6 altPSM altPSM Binary: Sigma=0.6 Binary: Sigma=0.6 PS: Sigma=0.35 PS: Sigma=0.35 OPC Style: Aggressive Simulation-Based OPC OPC Style: Aggressive Simulation-Based OPC PSM Style: NTI Double Exposure altPSM PSM Style: NTI Double Exposure altPSM NOT A Motorola process NOT A Motorola process Not lithographically refined or RET optimized Not lithographically refined or RET optimized

SEQUOIA Experimental Structure 32-bit Adder scaled to 150nm 32-bit Adder scaled to 150nm 4285 MOSFETs / CMOS technology 4285 MOSFETs / CMOS technology Lithography simulation performed full- structure Lithography simulation performed full- structure K-T/Finle -Prolith

SEQUOIA Defocus Effect BIM – 0.1um steps BIM 0-Def 0.2-Def 0.1-Def 0.4-Def 0.3-Def

SEQUOIA RET Effects BIM,BIM+OPC,PSM+OPC BIM, 0-Def BIM, 0.3-DefBIM+OPC, 0.3-DefPSM+OPC, 0.3-Def BIM+OPC, 0.4-DefPSM+OPC, 0.4-Def BIM, 0.4-Def

SEQUOIA Timing Results BIM First Technique – (Rachids gate averaging) Primarily a catastrophic Yield issue Leakage from line end shortening not considered Some transistors are outside of the model bounds SPICE Results

SEQUOIA Electrical Analysis of Proximity Effects Active devices (MOSFETs) responsible for circuit variability Active devices (MOSFETs) responsible for circuit variability Root cause of variability in sub- 130nm mosfets is MOSFET geometry (CD control) Root cause of variability in sub- 130nm mosfets is MOSFET geometry (CD control) Geometry is the result of mostly deterministic effects and predictable Geometry is the result of mostly deterministic effects and predictable Line-end pullback causes MOSFET leakage -> Yield Problem

SEQUOIA Impact of Process Variation Process variation causes image degradation Process variation causes image degradation Defocus process window is important for manufacturability Defocus process window is important for manufacturability Shown is the aerial image of the poly layer at increasing defocus Shown is the aerial image of the poly layer at increasing defocus Gate length variation and line-end pullback cause MOSFET parameter variation and failure Gate length variation and line-end pullback cause MOSFET parameter variation and failure Defocus degrades image No defocus 0.2um defocus

SEQUOIA Electrical Impact of Proximity Effects Proximity effects cause distortion depending on shape and environment of features Proximity effects cause distortion depending on shape and environment of features Short poly segments (small mosfet W) print differently from long ones Short poly segments (small mosfet W) print differently from long ones Proximity of other gates impacts gate shape and electrical performance Proximity of other gates impacts gate shape and electrical performance Context of a mosfet must be considered when predicting its properties Context of a mosfet must be considered when predicting its properties Defocus degrades image 0.15um defocus 0.2um defocus

SEQUOIA MOSFET Variability and Yield Defocus causes the gate length distribution to widen and shift to shorter gates Defocus causes the gate length distribution to widen and shift to shorter gates Circuit failure results from strong MOSFET parameter variation Circuit failure results from strong MOSFET parameter variation In extreme cases Source/Drain shorts (=very short gates) cause functional failure In extreme cases Source/Drain shorts (=very short gates) cause functional failure MOSFET Gate Lengths MOSFET Idsat 0.1um defocus 0 defocus 0.1um defocus 0 defocus

SEQUOIA Failure Outside Process Window Failure is observed as zero-length MOSFET by the verification tool Failure is observed as zero-length MOSFET by the verification tool SPICE timing analysis confirms circuit failure in this case SPICE timing analysis confirms circuit failure in this case Statistical analysis of MOSFET distribution across process window can be used to predict manufacturability Statistical analysis of MOSFET distribution across process window can be used to predict manufacturability MOSFET Gate Lengths 0.2um defocus Zero-length gates: Failures

SEQUOIA Conclusions Current state-of-art EDA design and verification tools have insufficient predictive performance capability in the Nanometer Era – Timing, SI, Race Conditions… +/- %100 These factors are also responsible in great part for costly fabrication re-spins – >%30 !. Failure Costs are high! Residual design-to-silicon distortions are a fact of life and must be accounted for in Nanometer Era Design and verification tools must account for increased process and device physics entanglement. Verification must consider the impact of process proximity and process variation on circuit performance Continuation of historical cycle, impact however is greater now than ever before A novel verification methodology is proposed as a unique new adjunct to DFM and MSO flows to reduce costly re-spins and improve inherent design quality and manufacturability. Catch Potential Re-Spin Failures Before Mask and Silicon !

SEQUOIA Acknowledgements Thank you Chris and Ed at KLA-Tencor/Finle for RC Pack use of Prolith for Gold-Standard confirmation and future work Thank you Chris and Ed at KLA-Tencor/Finle for RC Pack use of Prolith for Gold-Standard confirmation and future work Thank you Vinod and Fabio at Numerical Technologies for RC Pack use of IC Workbench for confirmation and future work Thank you Vinod and Fabio at Numerical Technologies for RC Pack use of IC Workbench for confirmation and future work

SEQUOIA Additional Supportive Materials

SEQUOIA Naive Simulation-based OPC Naive Simulation-based OPC Can make pretty pictures on silicon but impact the real process window Can make pretty pictures on silicon but impact the real process window At some level of k1, the context of the circuit and the device must be considered carefully At some level of k1, the context of the circuit and the device must be considered carefully Many digital circuits are very forgiving of some levels of distortion.. but unforgiving of others Many digital circuits are very forgiving of some levels of distortion.. but unforgiving of others Analog circuits/devices have their own special consideration Analog circuits/devices have their own special consideration Increased design-process integration care must be taken … its not just about making pretty pictures on silicon Increased design-process integration care must be taken … its not just about making pretty pictures on silicon Judicious and minimal usage of OPC Judicious and minimal usage of OPC Optimization target must be performance & Yield across Process-window. Optimization target must be performance & Yield across Process-window.

SEQUOIA Important issues for Designers, EDA, Maskmakers, lithographers, device designers, manufacturing… Entanglement of traditionally separable entities. Entanglement of traditionally separable entities. The determination of which features are dimensionally and visually good enough must be done on the basis of the feature function and IC operational and manufacturing requirements. The determination of which features are dimensionally and visually good enough must be done on the basis of the feature function and IC operational and manufacturing requirements. Visual metrics are no longer sufficient Visual metrics are no longer sufficient This era require new tools, new standards, new infrastructure….. This era require new tools, new standards, new infrastructure….. For EDA…Its not just about wire RLC and parasitics For EDA…Its not just about wire RLC and parasitics

SEQUOIA Acknowledgements Thank you Chris and Ed at KLA-Tencor/Finle for RC Pack use of Prolith for Gold-Standard confirmation and future work Thank you Chris and Ed at KLA-Tencor/Finle for RC Pack use of Prolith for Gold-Standard confirmation and future work Thank you Vinod and Fabio at Numerical Technologies for RC Pack use of IC Workbench for confirmation and future work Thank you Vinod and Fabio at Numerical Technologies for RC Pack use of IC Workbench for confirmation and future work