CS M51A/EE M16 Winter’05 Section 1 Logic Design of Digital Systems Lecture 4 January 24 W’05 Yutao He yutao@cs.ucla.edu 4532B Boelter Hall http://courseweb.seas.ucla.edu/classView.php?term=05W&srs=187154200 CSM51A/EEM16-Sec.1 W’05 Y. He @ 2/16/2019

Outline Administrative Matters Recap – Switching Functions/Expressions Chapter 3. Combinational IC’s CMOS Circuit Technology Summary

Administrative Matters Quiz #1 Is graded Will be handed back during the break Homework #3 Is posted Homework #2 Solution Will be posted tomorrow

Review - Spec. of S. F. XH YH What are inputs? How many are there? High-Level Spec FH XH YH Encoding Decoding Binary-Level Spec FB n m xB yB What are inputs? How many are there? What are outputs? How many are there? What are the relationships between them? How many bits are required for inputs/outputs? Which encoding schemes are used for inputs/outputs? What are the switching functions/truth tables?

Review – Switching Algebra Switching functions NOT, AND, OR, NAND, NOR, XOR Axioms and theorems of Boolean algebra Proofs by re-writing Incompletely specified Functions Expression equivalence

Bruin Teaser – S. F. 1-set notation: F(A,B,C) = A B C F 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 - 1 1 1 1 1-set notation: F(A,B,C) = 1-set(1,3,5,7) + d.c.-set(6) 0-set notation: F(A,B,C) = 0-set(0,2,4) + d.c.-set(6) CSP: F(A,B,C) = m1 + m3 + m5 + m7 + d.c.6 m-notation: F(A,B,C) = m(1,3,5,7) + d.c.(6) CPS: F(A,B,C) = M0 • M2 • M4 • d.c.6 M-notation: F(A,B,C) = M(0,2,4) •  d.c.(6) m1 = A’ • B’ • C M2 = A + B’ + C

Where Do We Stand? Idea Specification Logic Design Physical Design Fabrication CS EE

Overview of Physical Components Integrated Circuits (ICs), a.k.a. chips Control Logic (CL), memory elements, analog interfaces. Printed Circuit Boards (PCBs) Substrate for ICs and interconnection, distribution of CLK, Vdd, and GND signals, heat dissipation. Power Supplies Converts line AC voltage to regulated DC low voltage levels. Chassis (racks, cases, ...) Holds boards, power supply, provides physical interface to user or other systems. Connectors and Cables (RJ-45s, USBs, Firewires).

Integration Circuits (ICs) The patent application for IC technology is filed by Jack Kirby on July 20, 1959. Primarily Crystalline Silicon 1mm - 25mm on a side 100 - 100M transistors 25 - 25M "gates" 3 - 10 conductive layers 2004 - feature size ~ 0.13um = 0.13 x 10-6 m

Moore’s Law “Number of transistors on a chip doubles every 18 months.”

Level of Integration

Representation of Binary Variables How to represent 0 and 1 with physical phenomena? Technology Technology State 0 State 1 Pneumatic logic Fluid at low pressure Fluid at high pressure Relay logic Circuit open Circuit closed Bipolar (TTL) 0.0-0.8 volts 2.0-5.0 volts CMOS logic 0.0-0.8 volts 2.0-3.3 volts Dynamic memory Discharged capacitor Charged capacitor Nonvolatile memory (erasable) Electrons trapped Electrons released Programmable ROM Fuse blown Fuse intact Bubble memory No magnetic bubble Bubble present Magnetic tape/disk Flux direction “North” Flux direction “South” Compact Disc No pit Pit Fiber Optics Light off Light on Quantum Computing nuclear spin, probability amplitudes

Switch Logic close switch (if A is “1” or asserted) to turn on the light bulb (Z) A Z open switch (if A is “0” or unasserted) to turn off the light bulb (Z) A Z Z = A

Switch Logic (Cont.) Implement more complex switching functions in switch logic: A B A B Z = A OR B Z = A AND B To implement switching functions with switch logic: Determine whether or not a conducting path exists to light the light bulb. Use a light bulb (output of the network) to set other switches (inputs to another network). Connect together switching networks.

Transistor Logic Modern digital systems are based on transistor technology Semiconductor forms the major material of transistors There are two popular transistor technologies: Bipolar (TTL) CMOS Transistors act as voltage-controlled electronic switches

Voltage Regions 0.0V - 0.8V 2.0V - 3.3V

Positive/Negative Logic Positive logic “1” maps to VH “0” maps to VL Negative logic “1” maps to VL “0” maps to VH

MOS Transistor MOS stands for Metal-Oxide Semiconductor There are two types of MOS transistors: NMOS transistor PMOS transistor If VAC > VT, A is connected to B If VAC < VT, A is disconnected to B. If VBC > VT, A is connected to B If VBC < VT, A is disconnected to B. Physical Behavior If C=1, the switch is closed (ON) If C=0, the switch is open (OFF) If C=1, the switch is open (OFF) If C=0, the switch is close (ON) Logic Behavior

CMOS NOT Gates CMOS - Complementary MOS: NMOS and PMOS appear in pair Vin = VH Vout = VL

CMOS NOT Gates CMOS - Complementary MOS: NMOS and PMOS appear in pair Vin = VL Vout = VH Vin Vout VL VH VH VL x z 0 1 1 0

CMOS NAND Gates 1

CMOS NAND Gates 1 1

CMOS NAND Gates 1 1

CMOS NAND Gates 1

CMOS NOR Gates

CMOS AND/OR Gates

z equals to high impedance (Z) Transmission Gates 1 z = x 1 z equals to high impedance (Z)

XOR Gates

Physical Parameters Complexity parameters Timing Parameters Size Fan-in Fan-out Timing Parameters Propagation delay Rise time Fall time Load parameters Load factor Fanout factor Total load

Complexity Parameters Size Number of equivalent unit gates Fanin Number of inputs to a logic gate Fanout Number of branches that an output is connected to G1 G2 G3 G1 G2 G3 Fanin 2 3 2 Fanout 2 ? ?

Transition Time Changes in input/output values cannot be finished instantly

Propagation Delays Output values cannot be changed instantaneously as the change in input values.

Effect of Load Load affects timing parameters of an IC. An IC cannot be overloaded. The simple load model

Load Calculation Standard Load Load factor Total load Fanout factor is defined for each CMOS family as the base unit Load factor is the load of the gate inputs usually given in the data sheet Total load is the sum of the load factors of all the inputs connected to one output Fanout factor is the maximal load that one output can take

Load Calculation - Example

Three-State Driver (Buffers) Symbol Function Implementation

Three-State Driver - Applications

The Data Sheet of A Logic Family

Summary CMOS is the dominated technology for semiconductor industry Logic gates can be implemented by CMOS devices Concerns in the digital design: Propagation delays Transition times Load effects Some gates are construct to help relieve the concerns: Transmission Gates Three-state drivers

Next Lecture Chapter 5.1-5.3.3 Design of combinational Network