1. PROPAGATION DELAY

2. PROPAGATION DELAY Definition:
The delay time for the change in value of a signal to propagate from input to output.
output
input

3. …Propagation Delay
Operating Speed is inversely proportional to the longest propagation delay.

4. Propagation Delay Parameters …
t PHL The high-to-low propagation time
the delay measured from the reference voltage on the input voltage, IN, to the reference voltage on the output voltage, OUT, with the output voltage going from H to L.

5. Propagation Delay for an Inverter

6. Propagation Delay Parameters …
t PLH The low-to-high propagation time
the delay measured from the reference voltage on the input voltage, IN, to the reference voltage on the output voltage, OUT, with the output voltage going from L to H.

7. Propagation Delay Parameters …
t PD The propagation delay time
the maximum of the two delays,
t PLH and t PHL .

8. MULTILEVEL CIRCUITS

9. Digital Logic Gates

10. MULTILEVEL NAND CIRCUITS
Convert AND gates to NAND gates with AND-NOT symbols.
Convert OR gates to NAND gates with NOT-OR symbols.
Check all bubbles in the diagram
For every bubble that is not counteracted by another bubble along the same line:
Insert a NOT gate, or
Complement the input literal from its original appearance.

11. Logical Operations with NAND Gates

12. Alternative Graphics Symbols for NAND and NOT Gates

13. Three Ways to Implement F= AB + CD

14. Solution to Example 2.12

15. Fig 2.31

16. Fig 2.32

17. MULTILEVEL NOR CIRCUITS
The NOR operation is the dual of the NAND operation.
All procedures and rules for NOR logic are the dual of NAND logic.

18. Logic Operations with NOR Gates

19. Two Graphic Symbols for NOR Gate

20. Two-level Implementation
First level
Second level
Easiest if the simplified function is in POS form.

21. Procedure Outline … Simplify the function into POS form. Draw circuit:
Get from looping 0’s in K-map & complement the function.
Draw circuit:
1st level – OR gates - produce sum terms.
2nd level – AND gate – produce product terms.

22. … Procedure Outline Transformation of AND-OR diagram to NOR diagram:
Change OR gates to NOR gates, using OR-NOT symbol.
Change AND gates to NOR gates, using NOT-AND symbol.
A single lateral going into the 2nd level gate must be complemented, or else a NOT gate must be inserted.

23. Example 1 Implement this function with NOR gates:
F = (A + B) (C + D) E

24. Implementing F= (A+B)(C+D)E with NOR Gates

25. Multilevel Implementation of NOR gates
Similar steps to NAND gates

26. Procedure Outline … Transformation of AND-OR diagram to NOR diagram:
Change OR gates to NOR gates, using OR-NOT symbol.
Change AND gates to NOR gates, using NOT-AND symbol.
Any bubbles that is not compensated for by another bubble along the same line, needs an inverter or the complementation of the input lateral from its original appearance.

27. Example 2 Implement this function with NOR gates:
F = (A.NB + NA.B) . E . (C + ND)

28. Implementation with NOR Gates

29. EXCLUSIVE OR-GATES

30. EX-OR GATE X  Y = X.Y + X.Y Equals to 1 if exactly one input
is equal to 1.

31. 2-Input Exclusive-OR Constructed with NAND Gates

32. EX-NOR GATE (X  Y) = X.Y + X.Y
Equals to 1 if both X and Y are equal to 1 or if both are equal to 0.

33. ODD FUNCTION EX-OR gates with 3 or more inputs. X  Y  Z
= X.NY.NZ + NX.Y.NZ + NX.NY.Z + X.Y.Z
Equals to 1 if only one input is equal to 1 or if all 3 inputs are equal to 1.

34. EX-OR with 3 or more inputs
An odd number of inputs must be equal to 1.
Multiple input EX-OR gates is defined as the “odd function”.
See K-maps on next page.

35. Maps for Multiple-Variable Odd Function
Minterms whose binary values
have an odd number of 1’s

36. Parity Generation & Checking
Odd and even functions are very useful
In systems that require:
Error Detection & Correction Codes.
In the transmission of binary information.

37. Parity Bit
Is an extra bit included with a binary message to make the number of 1’s either odd or even.
The message, including the parity bit, is transmitted and then checked for errors at the receiving end.
An error is detected if the parity of the data bits in the message does not correspond to the parity bit transmitted.

38. Parity Generator & Checking
Parity generator circuit.
Generates the parity bit in the transmitter.
Parity checker circuit.
Checks the parity in the receiver.

39. Example
3-bit message to be transmitted with an even parity bit.

40. Truth Table for an Even Parity Generator

41. Even Parity Generator …
X, Y and Z – message inputs.
P, the parity bit, must be generated to make the total number of 1’s even.
From the TT, P is equal to 1 for the minterms having an odd number of 1’s.
P is an odd function.

42. … Even Parity Generator
 P, being an odd function, can be expressed as:
P = X  Y  Z
as in Fig (a).

43. Parity Checker … To check for errors in transmission.
As the information was transmitted with even parity, all 4 bits received must have an even number of 1’s.
Error is detected if these bits have an odd number of 1’s.
C = X  Y  Z  P

44. … Parity Checker C = X  Y  Z  P IS an odd function,
can be implemented with
4-input EX-OR gates,
as in Fig (b).

45. Multiple-Input Odd Functions

46. …Odd Function
A function with an even number of 1’s is the complement of an odd function.

47. 2-8 INTEGRATED CIRCUITS Digital circuits are constructed with ICs.
Contains components (transistors) that form the logic gates.
The gates are interconnected to form the complete circuit.
Advances in technology leads to increase in number of gates in an IC.

48. Levels of Integration SSI, Small Scale Integration.
Less than 10 gates.
MSI, Medium Scale Integration.
10 to 100 gates.
LSI, Large Scale Integration.
100 to a few thousand gates.
VLSI, Very Large Scale Integration.
Several thousand to over 100 million gates.

49. Digital Logic Families …
RTL – earliest, obsolete.
DTL – earliest, obsolete.
TTL – widely used.
ECL – high-speed operations.
MOS – high component density.
CMOS – low power consumption.

50. … Digital Logic Families
BiCMOS – high-current, high-speed.
GaAs – very high speed.

51. Parameters of IC Characteristics
Fan-in.
Fan-out.
Noise margin.
Power dissipation.
Propagation delay.

52. Positive and Negative Logic
Positive logic
H represents logic 1.
Negative logic
L represents logic 1.

53. Signal Assignment and Logic Polarity

54. Demonstration of Positive and Negative Logic

55. Negative logic
Notice the triangles used to indicate negative polarity.

56. Transmission Gate (TG)
An electronic switch for connecting and disconnecting 2 points in a circuit.
C and NC are the control signals.
X and Y are the signals to be connected or disconnected.

57. Transmission Gate (TG)