Gate Level Minimization Digital Logic Design Gate Level Minimization

Four-Variable Map 16 minterms (and squares) for 4 variables. One square represents one minterm, giving a term with four literals. Two adjacent squares represent a term with three literals. Four adjacent squares represent a term with two literals. Eight adjacent squares represent a term with one literal. Sixteen adjacent squares produce a function that is always equal to 1. No other combination of squares can simplify the function.

Example 5 Simplify F(w,x,y,z)=Σ(0,1,2,4,5,6,8,9,12,13,14) F(w,x,y,z)=y’+w’z’+xz’

Example 6 Simplify F=A’B’C’+B’CD’+A’BCD’+AB’C’ F=B’D’+B’C’+A’CD’

Prime Implicant In choosing adjacent squares in a map, we must ensure that all the minterms of the function are covered when we combine the squares the number of terms in the expression is minimized there are no redundant terms (i.e., minterms already covered by other terms) A product term obtained by combining the maximum possible number of adjacent squares. If a minterm is covered by only one prime implicant, that prime implicant is said to be essential.

Example F(A,B,C,D)=Σ(0,2,3,5,7,8,9,10,11,13,15)

Five-Variable Map Not simple, is not usually used. 5 variables, 32 squares.

Example 7 Simplify F(A,B,C,D,E)=Σ(0,2,4,6,9,13,21,23,25,29,31) F=A’B’E’+BD’E’+ACE

Product-of-Sums Simplification Mark the empty squares by 0’s. Combine them (as we did for sum-of-products) We obtain F’ (complement of the function) Take the complement of F’ ((F’)’) to obtain F.

Example 8 Simplfy F(A,B,C,D)=Σ(0,1,2,5,8,9,10) F=B’D’+B’C’+A’C’D F’=AB+CD+BD’ => F=(A’+B’)(C’+D’)(B’+D)

Example 8 gate impl. Two different implementations of the same function.

Don’t Care Conditions In practice’ some combinations are not specified as 1’s or 0’s. Four bit binary codes has six unused combinations. Functions having unspecified outputs are called incompletely specified functions. We don’t care the unspecified minterms These minterms are called don’t-care conditions. They can be used for minimization. They are indicated as X’s in the map. They can be assumed as 1’s or 0’s to have best simplification.

Example 9 Simplify F(w,x,y,z)=Σ(1,3,7,11,15) having don’t care conditions d(w,x,y,z)= Σ(0,2,5)

Example: We want to build the lamp logic for a stationary bicycle exhibit at the local science museum. As a rider increases his pedaling speed, lamps will light on a bar graph display. No lamps will light for no motion. As speed increases, the lower lamp, L1 lights, then L1 and L2, then, L1, L2, and L3, until all lamps light at the highest speed. Once all the lamps illuminate, no further increase in speed will have any effect on the display. A small DC generator coupled to the bicycle tire outputs a voltage proportional to speed. It drives a tachometer board which limits the voltage at the high end of speed where all lamps light. No further increase in speed can increase the voltage beyond this level. This is crucial because the downstream A to D (Analog to Digital) converter puts out a 3-bit code, ABC, 23 or 8-codes, but we only have five lamps. A is the most significant bit, C the least significant bit. The lamp logic needs to respond to the six codes out of the A to D. For ABC=000, no motion, no lamps light. For the five codes (001 to 101) lamps L1, L1&L2, L1&L2&L3, up to all lamps will light, as speed, voltage, and the A to D code (ABC) increases. We do not care about the response to input codes (110, 111) because these codes will never come out of the A to D due to the limiting in the tachometer block. We need to design five logic circuits to drive the five lamps.

NAND and NOR Implementation Generally used for circuit design Easier to fabricate. Basic gates Other functions can be generated from them. Rules have been developed to convert functions to NAND and NOR only implementations.

NAND Circuits NAND gate is universal Any digital system can be implemented with it. AND, OR and NOT can be implemented with NANDs.

Two graphic symbols of NAND

Two-Level Implementation Have the function in sum-of-product form. Put bubbles (inverters) to have two different representations of NAND gate Either AND-invert or Invert-OR

Example: F=AB+CD

Example 10 Implement F(x,y,z)=Σ(1,2,3,4,5,7) with only NAND gates.

Multilevel NAND Circuits 1. Convert all AND gates to NAND gates with AND-invert graphic symbols. 2. Convert all OR gates to NAND gates with invert-OR graphic symbols. 3. Check all the bubbles in the diagram. For every bubble that is not compensated by another small circle along the same line, insert an inverter (a one-input NAND gate) or complement the input literal. F=A(CD+B)+BC’

NOR Implementation Dual of NAND operation

Example: F=(A+B)(C+D)E

Example: F=(AB’+A’B)(C+D’)

Exclusive-Or (XOR) Function 1 if only x is one or if only y is 1 XNOR 1 if both inputs are 1 or both inputs are 0 Some identities of XOR

XOR Implementations Exclusive-OR operation is both commutative and associative; that is;

Odd Function The exclusive-OR operation with three or more variables can be converted into an ordinary Boolean function by replacing the ⨁symbol with its equivalent Boolean expression. In particular, the three-variable case can be converted to a Boolean expression as follows: The Boolean expression clearly indicates that the three-variable exclusive-OR function is equal to 1 if only one variable is equal to 1 or if all three variables are equal to 1. Contrary to the two-variable case, in which only one variable must be equal to 1, in the case of three or more variables the requirement is that an odd number of variables be equal to 1. As a consequence, the multiple-variable exclusive-OR operation is defined as an odd function.

Odd and Even Functions for XOR and XNOR

Logic Diagram of odd and even functions

Parity Generation A parity bit is an extra bit included with a binary message If number of 1’s is odd, parity bit is 1; else 0. The circuit that generates the parity bit in the transmitter is called parity generator. Parity bit can be generated using XOR function.

3-Bit Parity Generator

Parity Checker Bits are transmitted to the destination with parity. The circuit that checks the parity in the receiver is called a parity checker. Parity checker can be implmeneted with XOR gates.

3-Bit Parity Checker