2 3.1 Introduction The purposes of this chapter To understand the underlying mathematical description and solution of the problemTo enable you to execute a manual design of simple circuitsTo prepare you for skillful use of modern design toolsIntroduce a HDL that is used by modern design tools
3 3.2 The Map Method Karnaugh map (K-map) Pictorial form of a truth tableTo present a visual diagram of a function expressed in standard form
12 The Adjacent Squares of Four-Variable Map One square: one minterm, a term of four literalsTwo adjacent squares: a term of three literalsFour adjacent squares: a term of two literalsEight adjacent squares: a term of one literalSixteen adjacent squares: 1
15 PI and EPI A prime implicant(PI) An essential PI (EPI) a product term obtained by combining the maximum possible number of adjacent sqaures in the K-mapAn essential PI (EPI)If a minterm in a square is covered by only one PI.
25 How to express the Table 3-2 (con’t) F(x,y,z) = ∑ (1,3,4,6)F(x,y,z) = ∏ (0,2,5,7)
26 Map for the Function of Table 3-2 F= x’z+xz’F’=xz+x’z’ F=(x’+z’)(x+z)
27 3.6 Don’t Care ConditionsA don’t care minterm is a combination of variables whose logical value is not specified.The don’t care minterms may be assumed to be either 0 or 1.An X is used for representing the don’t care minterm.
52 Logic Diagram of a Parity Generator and Checker
53 3.10 Hardware Description Language (HDL) HDL : a documentation languageLogic simulator: representation of the structure and the behavior of a digital logic systems through a computerLogic synthesis: the process of driving a list of components and their connections from the model of a digital system described in HDL
54 Two Standard HDLs Supported by IEEE VHDLVerilog HDL : is chosen for this book
55 Verilog HDL module endmodule // : comment notation input output wire and or not# time unit`timescale: compiler directive