1. Karnaugh Map
and
Circuit Design

2. Four Variables MAP
The map minimization for four–variable Boolean function is similar to the method used to minimize three variable function.
Adjacent squares are defined to be square next to each other.
In addition, the map is considered to lie on a surface with the top and bottom edge, as well as the right and left edges touching each other to perform adjacent squares.
For example, m0 is adjacent to m2 and m4 is adjacent to m6 because the minterms differ by one variable. y yz wx 00 01 11 10 m0 m1 m3 m2 m4 m5 m7 m6
m12
m13
m15
m14 m8 m9
m11
m10
w’x’y’z’
w’x’y’z
w’x’yz
w’x’yz’
w’xy’z’
w’xy’z
w’xyz
w’xyz’
wxy’z’
wxy’z
wxyz
wxyz’
wx’y’z’
wx’y’z
wx’yz
wx’yz’ 00 01 x 11 w 10 z

3. This can be proved by:
m0 + m2 = w’x’y’z’ + w’x’yz’ = w’x’z’(y’+y) = w’x’z’
m4 + m6 = w’xy’z’ + w’xyz’ = w’xz’ (y’+y) = w’xz’
One square represents one minterm given a term of four literals
Two adjacent squares represents a term of three literals
Four adjacent squares represents a term of two literal
Eight adjacent squares takes one literal
Sixteen adjacent squares represent the function equal to 1.

4. Example: Simply the Boolean function
F (w,x,y,z) = S (0,1,2,4,5,6,8,9,12,13,14)
Since the function has four variables, a four variable map must be used.
The minterm listed in the sum are marked by 1’s in the map.
8 adjacent squares marked with 1’s can be combined to form the one literal term y’.
The remaining three 1’s on the right cannot be combined to give a simplified term
They must be combined as two or four adjacent squares y yz wx 00 01 11 10 1 m0 m1 m3 m2 m4 m5 m7 m6
m12
m13
m15
m14 m8 m9
m11
m10 00 01 x 11 w 10 z

5. The top two 1’s on the right are combined with the top two 1’s on the left to give the term w’z’
Note that it is permissible to use the same square more than once
Now we are left with the square marked by 1 in the third row (m14)
Instead of taking this square alone (which will give a term of 4 literals), we combine it with squares that already used to form an area of 4 adjacent squares
These squares make up the two middle rows and the two end columns giving the term xz’
The simplified function is
F = y’ + w’z’ + xz’

6. 5 variable map
Maps for more than four variables are not simple to use. A five variable map needs 32 squares and a 6 variable map needs 64 squares
When the number of variables becomes large, the number of squares becomes excessively large and the geometry for combining adjacent squares become involved
Consider the following 5 variable map:
A = 0
A = 1 D D DE BC DE BC 00 01 11 10 00 01 11 10 m0 m1 m3 m2 m4 m5 m7 m6
m12
m13
m15
m14 m8 m9
m11
m10
m16
m17
m19
m18
m20
m21
m23
m22
m28
m29
m31
m30
m24
m25
m27
m26 00 00 01 01 C C 11 11 B B 10 10 E E

7. The five variable map consists of two four variables maps with variables A, B, C, D and E
Variable A distinguishes between the two maps as indicated on the top of the diagram
The left hand side four variable map represents the 16 squares (minterms 0-15) where A=0 and the other 4 variable map represents the squares (minterms 16-31) where A=1
Each four variable map, retains the previously defined adjacency when taken separately
In addition, each square in the A=0 map is adjacent to the corresponding square in the A=1 map
For example, m4 is adjacent to m20 and m15 is adjacent to m31

8. ` Example: Simplify the Boolean function:
F (A, B, C, D, E) = (0, 2, 4, 6, 9, 13, 21, 23, 25, 29, 31)
Four adjacent squares in the A=0 map, are combined to give the three literal term A’B’E’
The two squares in column 01 and the last two rows are combined to both part of the map to give three literal term BD’E
The term ACE is obtained from the four adjacent square that are entirely within the A=1 map
A = 0
A = 1 D D DE BC DE BC 00 01 11 10 00 01 11 10 1 1 00 00 01 01 C C 11 11 B B 10 10 E E

9. NAND and NOR implementation
Digital circuit are frequently constructed with NAND or NOR gates rather than AND or OR gates
Because of importance of NAND and NOR gates in the design of digital circuit, rules and procedures have been developed for the conversion from Boolean function in terms of AND, OR and NOT into equivalent NAND and NOR logic diagrams

10. Implementing AND with NAND Implementing OR with NAND
NAND Circuits
The NAND gate is set to be the universal gate because any digital system can be implemented with it
To show that any Boolean function can be implemented with NAND gate we need to show that the logical operations of AND, OR and COMPLEMENT can be obtained with NAND gate only as follows:
Implementing
Complement with NAND x x’
Implementing AND with NAND y x
(xy)’
AND xy x x’
Implementing OR with NAND
(x’y’)’ = x + y OR y y’

11. These three circuit are equivalent and implement the function F.
To implement a Boolean function with NAND gates, the function should be in sum of product forms.
To see the relationship between the sum of product expression and its equivalent NAND implementation, consider this function.
F = AB+CD
These three circuit are equivalent and implement the function F. 1 A B C D F 1 3 1 2 A B C D F A B C D F
OR Invert gate

12. The function is implemented with AND and OR gates
The function is implemented with AND and OR gates. The AND gates are replaced by NAND gates and the OR gates is replaced by OR-invert graphic symbol (another symbol for NAND gate).
Remember that a bubble denotes complementation and two bubble along the same line represent double complementation, so both can be removed.
Removing the bubbles on the second circuit produces the first one, so both diagram are the same.
The NAND representation on third circuit can be verified algebraically (by DeMorgan law) that represents the same function.
F= ((AB)’(CD)’)’ =AB +CD

13. Implement the following Boolean function with NAND gates
Example
Implement the following Boolean function with NAND gates
F(x,y,z) = (1,2,3,4,5,7)
The first step is to simplify the function in sum of product, using three variable map
F = xy’ + x’y + z y yz x 00 01 11 10 1 x 1 z x y’ x’ y F z’

14. Draw NAND gate for each product term of the expression that has at least two literals. This constitute the first level gates.
Draw single gate using the NAND gate or OR-invert for second level, with input coming from the output of first level gates.
A term with a single literal requires an inverter in the first level. However, if the single literal is complemented, it can be connected directly to an input of second level NAND gate

15. Different digital circuits
Logic circuits for digital system may be combinational or sequential
A combinational circuit consist of logic gates whose outputs at any time are determined from the present combination of input.
Sequential circuit will be defined later in the course.

16. Design Procedure of Combinational Circuit
The design of combinational circuits starts from the specification of the problem that can be implemented in a logic circuit diagram or a set of Boolean function .
The procedure involves the following steps:
From the specifications of the circuit, determine the required number of inputs and outputs and assign a symbol to each
Derive the truth table that defines the required relationship between inputs and outputs.
Obtain the simplified Boolean function for each output as a function of the input variables
Draw the logic diagram and verify the correctness of the design.

17. This simple addition consist of four possible elementary operations:
Design of Binary Adder
The most basic arithmetic operation is the addition of two binary digits
This simple addition consist of four possible elementary operations:
0+0=0, 0+1=1, 1+0 =1 and 1+1=1 0
The first three operation produce a one digit number as result, but when both augends and addend bits are equal to 1, the binary sum consist of two digits (10).
The higher significant bit of this result is called a carry
The lower significant digit is sum
The combinational circuit that performs the addition of two bits is called half adder
Carry
Sum

18. Half Adder
Half adder circuit needs two binary inputs and produce two binary outputs.
The input variables are the augend and addend bits; the output variables are sum (s) and carry (c)
In this circuit x and y are input and S and C are the output
The truth table, the Boolean function and the logic circuit for half adder are:
S = x’y + xy’ ( from the truth table)
C = xy ( from the truth table) x y C S 1 x y’ S x’ y x C y

19. So the alternative circuit for half adder is:
Also by looking at truth table half adder can be implemented by an exclusive-OR and a AND gate.
S=x’y + xy’ = x + y
C = xy
So the alternative circuit for half adder is: S y x C

20. Full Adder
A full adder is a combinational circuit that form the arithmetic sum of three bits.
It consist of three inputs and two outputs
Two of the inputs are x and y, representing the two significant bits to be added.
The third input z is carry from the previous lower significant position.
Two output are sum(S) and carry(C)
the truth table and map for full adder are:
S = x’y’z+x’yz’+xy’z’+xyz C= xy+xz+yz
C= xy+xy’z+x’yz (not completely simplified) y y x y z C S 1 yz yz 11 01 11 01 x 00 10 x 00 10 1 1 x 1 x 1 z z

21. S=z’(xy’+yx’) + z(xy’+yx’)’ S= z’xy’+z’yx’+z[(xy’)’.(yx’)’]
The logic diagram of full adder can be implemented from expression for sum(S) and carry(C)
It also can be implemented from two half adder and one OR gate as shown below .
S=z + (x + y)
S =z + (xy’ + yx’)
S=z’(xy’+yx’) + z(xy’+yx’)’
S= z’xy’+z’yx’+z[(xy’)’.(yx’)’]
S= …………...+ z[(x’+y).(y’+x)]
S= z’xy’+z’yx’+zx’y’ + zyx
( the same as map’s result)
The carry output is:
C = z(xy’ + x’y) + xy
C = xy’z+x’yz + xy
( the same as map’s result )
The S output from the first half adder with the z are input for the exclusive OR for the second half adder giving the below function for S.
The C output from the first half adder with the C output from the second half adder ORed together giving the below function for C S y x C z

22. A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers.
It is implemented with full adders connected in cascade.
For adding two n bit binary numbers (A and B) n full adder is been used (one full adder for each two bits that needs to be added).
Consider adding two 4-bit binary numbers
A = and B = 0011
that is been implemented in circuit shown in the next slide
The input carry C0 is the least significant position and must be zero.
First adder gets the first bits of the two binary numbers plus input carry C0 and produce the sum (S0) and the carry (C1) which will be the input to the second adder
Second adder gets the second bits of the two binary numbers plus input carry C1 and produce the sum (S1) and the carry (C2) which will be the input to the third adder. And so on

23. Subscript i 3 2 1 0 Input carry 0 1 1 0 Ci Augend 1 0 1 1 Ai
Addend Bi
Sum Si
Output carry Ci+1 FA
A0=1
B3=0
A3=1
B2=0
A2=0
B1=1
A1=1
B0=1
C0=0
S3=1
S2=1
S1=1
S0=0
C3=0
C2=1
C1=1
C4=0