1. Fuw-Yi Yang1 數位系統 Digital Systems Department of Computer Science and Information Engineering, Chaoyang University of Technology 朝陽科技大學資工系 Speaker: Fuw-Yi Yang 楊伏夷 伏夷非征番, 道德經 察政章 (Chapter 58) 伏 者潛藏也 道紀章 (Chapter 14) 道無形象, 視之不可見者曰 夷

2. Fuw-Yi Yang2 Text Book: Digital Design 4th Ed. Chap 3 Gate-Level Minimization 3.1 Introduction 3.2 The Map Method 3.3 Four-Variable Map 3.4 Five-Variable Map 3.5 Production-of-Sums Simplification 3.6 Don't-Care Conditions 3.7 NAND and NOR Implementation 3.8 Other Two-Level Implementation 3.9 Exclusive-Or Function 3.10 Hardware Description Language

3. Fuw-Yi Yang3 Text Book: Digital Design 4th Ed. Chap 3.1 Introduction Gate-level minimization refers to the design task of finding an optimal gate-level implementation of the Boolean functions describing a digital circuit. It is important that a designer understand the underlying mathematical description and solution of a problem.

4. Fuw-Yi Yang4 Text Book: Digital Design 4th Ed. Chap 3.2 The Map Method Boolean expression may be simplified by algebraic means as discussed in Section 2.4. However, this procedure of minimization is awkward because it lacks specific rules to predict each succeeding step in the manipulative process. The map method (also known as the Karnaugh map or K-map) provides a simple, straightforward procedure for minimizing Boolean functions.

5. Fuw-Yi Yang5 Text Book: Digital Design 4th Ed. Chap 3.2 The Map Method — two-variable map Figure 3.1 Two-Variable map

6. Fuw-Yi Yang6 Text Book: Digital Design 4th Ed. Chap 3.2 The Map Method — two-variable map Figure 3.2 Representation of functions in the map

7. Fuw-Yi Yang7 Text Book: Digital Design 4th Ed. Chap 3.2 The Map Method — three-variable map Figure 3.3 Three-variable map

8. Fuw-Yi Yang8 Text Book: Digital Design 4th Ed. Chap 3.2 The Map Method — Example 3.1 Simplify the Boolean function F(x, y, z) =  (2, 3, 4, 5) Figure 3.4 F(x, y, z) =  (2, 3, 4, 5) = x'y + xy'

9. Fuw-Yi Yang9 Text Book: Digital Design 4th Ed. Chap 3.2 The Map Method — Example 3.2 Simplify the Boolean function F(x, y, z) =  (3, 4, 6, 7) Figure 3.5 F(x, y, z) =  (3, 4, 6, 7) = yz + xz'

10. Fuw-Yi Yang10 Text Book: Digital Design 4th Ed. Chap 3.2 The Map Method — Example 3.3 Simplify the Boolean function F(x, y, z) =  (0, 2, 4, 5, 6) Figure 3.6 F(x, y, z) =  (0, 2, 4, 5, 6) = z' + xy'

11. Fuw-Yi Yang11 Text Book: Digital Design 4th Ed. Chap 3.2 The Map Method — Example 3.4 a. Express F as a sum of minterms. b. Find the minimum SOP. Figure 3.7 F = A'C + A'B + AB'C + BC =  (1, 2, 3, 5, 7) = C + A'B

12. Fuw-Yi Yang12 Text Book: Digital Design 4th Ed. Chap 3.3 The Map Method — Four-Variable Map

13. Fuw-Yi Yang13 Text Book: Digital Design 4th Ed. Chap 3.3 The Map Method — Four-Variable Map

14. Fuw-Yi Yang14 Text Book: Digital Design 4th Ed. Chap 3.3 The Map Method — Example 3.5 Simplify F(w, x, y, z) =  (0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14) Figure 3.9 F =  (0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14) = y'+ w' z'+ x z'

15. Fuw-Yi Yang15 Text Book: Digital Design 4th Ed. Chap 3.3 The Map Method — Example 3.5

16. Fuw-Yi Yang16 Text Book: Digital Design 4th Ed. Chap 3.3 The Map Method — Example 3.6 Simplify F(A, B, C, D) = A'B'C' + B'CD' + A'BCD' + AB'C' Figure 3.10 F = A'B'C' + B'CD' + A'BCD' + AB'C' = B'C' + B'D' + A'CD' see next page

17. Fuw-Yi Yang17 Text Book: Digital Design 4th Ed. Chap 3.3 The Map Method — Example 3.6

18. Fuw-Yi Yang18 Text Book: Digital Design 4th Ed. Chap 3.3 The Map Method — Prime implicants In choosing adjacent squares in a map, we must ensure that (1) all the minterms of the function are covered when we combine the squares, (2) the number of terms in the expression is minimized, and (3) there are no redundant terms (i.e., minterms already covered by other terms).

19. Fuw-Yi Yang19 Text Book: Digital Design 4th Ed. Chap 3.3 The Map Method — Prime implicants A prime implicant is a product term obtained combining the maximum possible number of adjacent squares in the map. If a minterm in a square is covered by only one prime implicant, that prime implicant is said to be essential. Simplify F(A, B, C, D) =  (0, 2, 3, 5, 7, 8, 9, 10, 11, 13, 15) See next pages

20. Fuw-Yi Yang20 Text Book: Digital Design 4th Ed. Chap 3.3 The Map Method — prime Two essential prime implicants: BD and B'D'

21. Fuw-Yi Yang21 Essential prime implicants: BD and B'D' Prime implicants: AD, CD, B'C, and AB' F = BD+B'D' +CD+ AD OR BD+B'D' +CD+ AB' OR BD+B'D' + B'C+ AD OR BD+B'D' + B'C

22. Fuw-Yi Yang22 Text Book: Digital Design 4th Ed. Chap 3.5 Product-of-Sums Simplification Example 3.8 Simplify F(A, B, C, D) =  (0, 1, 2, 5, 8, 9, 10) into a. sum-of-products form, taking the procedures as described previously, i.e., group the squares marked by 1’s and combine them. b. product-of-sums form. Group the squares marked by 0’s and combine them, i.e., we obtain F ' in the form of sum-of-product. Because of the generalized DeMorgan’s theorem, the product-of-sums form is also obtained. Procedures see next page

23. Fuw-Yi Yang23 F=B'C' + B'D' + A'C'D' F' = AB + CD + BD' Applying DeMorgan’s theorem to F', F = (A' + B') + (C' + D') + (B' + D)

24. Fuw-Yi Yang24 F=B'C' + B'D' + A'C'D' F' = AB + CD + BD' Applying DeMorgan’s theorem to F', F = (A' + B') + (C' + D') + (B' + D) Implementation see next pages

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26. Fuw-Yi Yang26 Text Book: Digital Design 4th Ed. Chap 3.5 Product-of-Sums Simplification a. sum-of-products form b. product-of-sums form These two forms can also obtain from truth table, see next page.

27. Fuw-Yi Yang27 Text Book: Digital Design 4th Ed. Chap 3.5 Product-of-Sums Simplification F(x, y, z) =  (1, 3, 4, 6) F(x, y, z) =  (0, 2, 5, 7) = (x' + z') (x + z) See next page, note that we express F directly in the POS form. Table 3.2 xyzF 0000 m 0, M 0 0011 m 1, M 1 0100 m 2, M 2 0111 m 3, M 3 1001 m 4, M 4 1010 m 5, M 5 1101 m 6, M 6 1110 m 7, M 7

28. Fuw-Yi Yang28 F(x, y, z) =  (1, 3, 4, 6) F'(x, y, z) =  (0, 2, 5, 7) By DeMorgan’s Theorem F(x, y, z) =  (0, 2, 5, 7) = (x' + z') (x + z)

29. Fuw-Yi Yang29 Text Book: Digital Design 4th Ed. Chap 3.6 Don ’ t Care Conditions Functions that have unspecified outputs for some input combinations are called incompletely specified functions. In most applications, we simply don’t care what value is assumed by the function for the unspecified minterms. For this reason, it is customary to call the unspecified minterms of a function don’t care conditions. These don’t care conditions can be used on a map to provide further simplification of a Boolean expression.

30. Fuw-Yi Yang30 Text Book: Digital Design 4th Ed. Chap 3.6 Don ’ t Care Conditions Example 3.9 Simplify the Boolean function F(w, x, y, z) =  (1, 3, 7, 11, 15) which has the don’t care conditions d(w, x, y, z) =  (0, 2, 5).

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32. Fuw-Yi Yang32 Text Book: Digital Design 4th Ed. Chap 3.7 NAND and NOR Implementation Digital circuits are frequently constructed with NAND or NOR gates rather than with AND and OR gates. NAND and NOR gates are easier to fabricate with electronic components and are the basic gates used in all IC digital logic families. Because of the prominence of NAND and NOR gates in the design of digital circuits, rules and procedures have been developed for the conversion from Boolean functions given in terms of AND, OR, and NOT into equivalent NAND and NOR logic diagrams.

33. Fuw-Yi Yang33 Text Book: Digital Design 4th Ed. Chap 3.7 NAND and NOR Implementation -- NAND Circuits The NAND gate is said to be a universal gate because any digital system can be implemented with it.

34. Fuw-Yi Yang34 Text Book: Digital Design 4th Ed. Chap 3.7 NAND and NOR Implementation -- NAND Circuits A convenient way to implement a Boolean function with NAND gates is to obtain the simplified Boolean function in terms of Boolean operators and then convert the function to NAND logic. The conversion of an algebraic expression from AND, OR, and complement to NAND can be done by simple circuit manipulation technique that change AND-OR diagrams to NAND diagrams.(minterms)

35. Fuw-Yi Yang35 Text Book: Digital Design 4th Ed. Chap 3.7 NAND and NOR Implementation -- NAND Circuits Two equivalent graphic symbols for the NAND gate are shown below. It is convenient to use them in converting AND, OR, and NOT expressions into NAND expressions. See next page.

36. Fuw-Yi Yang36 Text Book: Digital Design 4th Ed. Chap 3.7 NAND and NOR Implementation -- Three ways to implement F = AB + CD (two-level) (x')' = x Implemented with NAND gates AND-OR Equivalent symbols of NAND

37. Fuw-Yi Yang37 Text Book: Digital Design 4th Ed. Chap 3.7 NAND and NOR Implementation -- Example 3.10 Two-level Implement F(x, y, z) =  (1, 2, 3, 4, 5, 7) with NAND gates. After simplification, F(x, y, z) = xy' + x'y + z AND-OR (x')' = x Implemented with NAND gates

38. Fuw-Yi Yang38 Text Book: Digital Design 4th Ed. Chap 3.7 NAND and NOR Implementation -- NAND Circuits--Multilevel There are occasions, however, when the design of digital systems results in gating structures with three or more levels. The most common procedure in the design of multilevel circuits is to express the Boolean function in terms of AND, OR, and complement operations. The function can then be implemented with AND and OR gares. After that, if necessary, it can be converted into an all-NAND circuit. See next page.

39. Fuw-Yi Yang39 Text Book: Digital Design 4th Ed. Chap 3.7 NAND and NOR Implementation -- NAND Circuits--Multilevel AND-OR (x')' = x

40. Fuw-Yi Yang40 NAND Circuits--Multilevel

41. Fuw-Yi Yang41 Text Book: Digital Design 4th Ed. Chap 3.7 NAND and NOR Implementation -- NOR Circuits The NOR gate is said to be a universal gate because any digital system can be implemented with it.

42. Fuw-Yi Yang42 Text Book: Digital Design 4th Ed. Chap 3.7 NAND and NOR Implementation -- NOR Circuits A convenient way to implement a Boolean function with NOR gates is to obtain the simplified Boolean function in terms of Boolean operators and then convert the function to NOR logic. The conversion of an algebraic expression from AND, OR, and complement to NOR can be done by simple circuit manipulation technique that change OR-AND diagrams to NOR diagrams. (maxterms)

43. Fuw-Yi Yang43 Text Book: Digital Design 4th Ed. Chap 3.7 NAND and NOR Implementation -- NOR Circuits Two equivalent graphic symbols for the NOR gate are shown below. It is convenient to use them in converting AND, OR, and NOT expressions into NOR expressions. See next page.

44. Fuw-Yi Yang44 Text Book: Digital Design 4th Ed. Chap 3.7 NAND and NOR Implementation -- NOR Circuits Implementing F = (A + B) (C + D) E with NOR gates Note that OR-AND Equivalent symbols of NOR

45. Fuw-Yi Yang45 Text Book: Digital Design 4th Ed. Chap 3.7 NAND and NOR Implementation -- NOR Circuits Implementing F = (AB' + A'B) (C + D') with NOR gates Note that OR-AND Equivalent symbols of NOR

46. Fuw-Yi Yang46 Text Book: Digital Design 4th Ed. Chap 3.8 Other Two-Level Implementations The types of gates most often found in integrated circuits are NAND and NOR gates. For this reason, NAND and NOR logic implementations are the most important from a practical point of view. Some NAND and NOR gates allow the possibility of a wire connection between the outputs of two gates to provide a specific logic function. This type of logic is called wired logic. See next pages

47. Fuw-Yi Yang47 Text Book: Digital Design 4th Ed. Chap 3.8 Other Two-Level Implementations Wired logic

48. Fuw-Yi Yang48 Text Book: Digital Design 4th Ed. Chap 3.8 Other Two-Level Implementations AND-OR-INVERT

49. Fuw-Yi Yang49 Text Book: Digital Design 4th Ed. Chap 3.8 Other Two-Level Implementations OR-AND-INVERT

50. Fuw-Yi Yang50 Text Book: Digital Design 4th Ed. Chap 3.8 Other Two-Level Implementations

51. Fuw-Yi Yang51 Text Book: Digital Design 4th Ed. Chap 3.8 Other Two-Level Implementations Example 3.11 Implement the function of the following map with the four 2-level forms listed in Table 3.3.

52. Fuw-Yi Yang52 Text Book: Digital Design 4th Ed. Chap 3.8 Other Two-Level Implementations Example 3.11 AND-NOR  AND-OR-NOT F' = x'y + xy' + z combined squares of the 0’s. Thus F = (F')' output gate NOR = OR+NOT

53. Fuw-Yi Yang53 Text Book: Digital Design 4th Ed. Chap 3.8 Other Two-Level Implementations Example 3.11 NAND-AND  AND-OR-NOT F' = x'y + xy' + z combined squares of the 0’s. Thus F = (F')' = (x'y + xy' + z)' = (x'y)' (xy')' z' output gate AND

54. Fuw-Yi Yang54 Text Book: Digital Design 4th Ed. Chap 3.8 Other Two-Level Implementations Example 3.11 OR-NAND  OR-AND-NOT F = x'y'z' + xyz' combined squares of the 1’s. Thus F = (F')' = ((x + y + z) (x' + y' + z))', or-and-not. output gate NAND = AND + NOT

55. Fuw-Yi Yang55 Text Book: Digital Design 4th Ed. Chap 3.8 Other Two-Level Implementations Example 3.11 NOR-OR  OR-AND-NOT F = x'y'z' + xyz' combined squares of the 1’s. Thus F = (F')' = ((x + y + z) (x' + y' + z))' = (x + y + z)' + (x' + y' + z)', output gate OR.

56. Fuw-Yi Yang56 Text Book: Digital Design 4th Ed. Chap 3.9 Exclusive-OR Function The exclusive-OR (XOR), denoted by the symbol , is a logical operation that performs the following Boolean operation: x  y = x'y + xy'. It can be shown that the exclusive-OR operation is both commutative and associative; that is, x  y = y  x and (x  y)  z = x  (y  z) = x  y  z. For implementation, see next pages.

57. Fuw-Yi Yang57 Text Book: Digital Design 4th Ed. Chap 3.9 Exclusive-OR Function — AND-OR-NOT implementation

58. Fuw-Yi Yang58 Text Book: Digital Design 4th Ed. Chap 3.9 Exclusive-OR Function -- NAND implementation

59. Fuw-Yi Yang59 Text Book: Digital Design 4th Ed. Chap 3.9 Exclusive-OR Function -- ODD Function x  y = x'y + xy' x  y  z = xy'z' + x'yz' + x'y'z + xyz The Boolean expression clearly indicates that the XOR functions are equal to 1 if and only if an odd number of variables equal to 1.

60. Fuw-Yi Yang60 Text Book: Digital Design 4th Ed. Chap 3.9 Exclusive-OR Function --Parity Generation and Checking

61. Fuw-Yi Yang61 Text Book: Digital Design 4th Ed. Chap 3.9 Exclusive-OR Function --Parity Generation and Checking x  Y  z  P  Four bits are transmitted

62. Fuw-Yi Yang62 Text Book: Digital Design 4th Ed. Chap 3.9 Exclusive-OR Function --Parity Generation and Checking x  y  z  P  Four bits are transmitted Check four lines (x, y, z, P) See next page

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64. Fuw-Yi Yang64 Text Book: Digital Design 4th Ed. Chap 3.10 Hardware Description Language HDL Example 3.1 module Simple_Circuit(A, B, C, D, E); output D, E; input A, B, C; wire w1; and G1(w1, A, B); not G2(E, C); or G3(D, w1, E); endmodule