EET 1131 Unit 11 Counter Circuits Read Kleitz, Chapter 12, skipping Sections 12-10 and 12-11. (Note that we are skipping Chapter 11.) Homework #11 and Lab #11 due next week. Quiz next week. -Handouts: Quiz #10, Unit 11 practice sheets. -We’re skipping Chapter 11.

Counting Counting is a very common operation in digital systems. Some examples on a macro-scale: Counting the number of times a microwave-oven button was pressed. Counting the number of objects that pass on a conveyor belt. Counting the number of cars entering or leaving a parking lot. Some examples on a micro-scale: Counting the number of bytes that enter from a modem. Counting the number of clock cycles since an internal control signal went HIGH. 2

Counting in Binary As you know, the binary count sequence follows a familiar pattern of 0’s and 1’s as described in Section 2-2 of the text. 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 LSB changes on every number. The next bit changes on every second number. The next bit changes on every fourth number.

Counting in Binary A counter can form the same pattern of 0’s and 1’s with logic levels. The first stage in the counter represents the least significant bit – notice that these waveforms follow the same pattern as counting in binary. LSB MSB

Two Basic Counter Designs You can build a counter by connecting flip-flops to each other. There are two standard ways to do this, one of which results in what is called an asynchronous counter, the other resulting in what is called a synchronous counter. See next slide…. -How does a single JK flip-flop in toggle mode behave? It’s a MOD-2 counter (or divide-by 2 counter) that counts from 0 to 1 and then recycles. -Basic idea for higher-MOD counters is to connect several flip-flops together in such a way that they count up from 0 to some terminal state, at which point they recycle back to 0. 5

Asynchronous versus Synchronous Counters 4-bit Asynchronous Counter: 4-bit Synchronous Counter: Do Practice Questions 1, 2. 6

Synchronous versus Asynchronous The synchronous/asynchronous distinction has different meanings: As applied to inputs: A change on a synchronous input doesn’t affect the outputs until the next active clock edge, but a change on an asynchronous input affects the outputs immediately. 7

Synchronous versus Asynchronous The synchronous/asynchronous distinction has different meanings: As applied to counters: in a synchronous counter, the outputs can all change at the same instant; but in an asynchronous counter, there’s a brief delay between the changing of the outputs. 8

Three bit Asynchronous Counter In an asynchronous counter, the clock is applied only to the first stage. Each subsequent stage gets its clock from the previous stage. The asynchronous counter shown is a three-bit counter (also called MOD-8 counter or divide-by-8 counter). It uses J-K flip-flops in the toggle mode. CLK K0 J0 Q0 C J1 J2 K1 K2 Q1 Q2 HIGH Note these are positive-edge-triggered flip-flops, that’s why clocks are driven from Q’ output. Waveforms are on the following slide…

Three bit Asynchronous Counter Notice that the Q0 output is triggered on the rising edge of the clock signal. The following stage is triggered from Q0. The rising edge of Q0 is equivalent to the falling edge of Q0. The resulting sequence is that of a 3-bit binary up counter. CLK Q0 Q1 Q2 Note: This idealized timing diagram ignores the propagation delays from one stage to the next. See next slide…

Propagation Delay Asynchronous counters are sometimes called ripple counters, because the stages do not all change together. For certain applications requiring high clock rates, this is a major disadvantage. Notice how delays are cumulative as each stage in a counter is clocked later than the previous stage. CLK Q0 Q1 Q2 Q0 is delayed by 1 propagation delay, Q1 by 2 delays and Q2 by 3 delays.

Terminology: Modulus and Divide-By CLK K0 J0 Q0 C J1 J2 K1 K2 Q1 Q2 HIGH As noted on an earlier slide, the three-bit counter shown here is also called a MOD-8 counter or a divide-by-8 counter. A counter’s modulus is the number of different values it can count through. The example shown has a modulus of 8. (The eight values are 000, 001, 010, 011, 100, 101, 110, 111.) Also, the signal at Q2 will have a frequency equal to one-eighth of the incoming clock frequency. That’s why we can call it a divide-by-8 counter. 12

The 74LS93 Asynchronous Counter The 74LS93 has one independent toggle J-K flip-flop driven by CLK A and three toggle J-K flip-flops that form an asynchronous counter driven by CLK B. The counter can be extended to form a 4-bit counter by connecting Q0 to the CLK B input. Two inputs are provided that clear the count. CLK B J0 J1 J2 J3 CLK A C C C C We’ve used this chip in Labs 1, 2, and 8. K0 K1 K2 K3 All J and K inputs are connected internally HIGH RO (1) RO (2) Q0 Q1 Q2 Q3

A Family of Four-Bit Asynchronous Counter ICs 7490 Four-bit decade counter (MOD 10) 7492 Four-bit divide-by-12 counter (MOD 12) 7493 Four-bit binary counter (MOD 16) Do Practice Questions 3, 4.

Asynchronous Decade Counter This counter uses a NAND gate to recycle the count sequence to zero after the 1001 state, resulting in a MOD-10 counter (or decade counter). Other truncated sequences can be obtained using a similar technique. CLR CLK K0 J0 Q0 C J1 J2 K1 K2 Q1 Q2 HIGH J3 K3 Q3 -Variation on the basic counter, except extra gates force the count back to 0 before it gets all the way up to 15. This is called a truncated sequence. Waveforms are on the following slide…

Asynchronous Decade Counter When Q1 and Q3 are HIGH together, the counter is cleared by a “glitch” on the CLR line. CLK Q0 Glitch Q1 Q2 Q3 CLR Glitch

BCD Decoder/Driver A special-purpose decoder is the 7447. This is a BCD-to-seven segment display with active LOW outputs. VCC BCD/7-seg The a-g outputs are designed for much higher current than most devices (hence the word driver in the name). BI/RBO BI/RBO BCD inputs Outputs to seven segment device LT LT RBI RBI 74LS47 GND

BCD Decoder/Driver Here the 7447 is an connected to an LED seven segment display. Notice the current-limiting resistors, required to prevent overdriving the LED display.

7447 BCD-to-7-Segment Decoder/Driver 4 input pins for BCD code. 7 output pins to control the seven segments of a 7-segment display. Also has a lamp test input. Also a ripple-blanking input and output to suppress leading or trailing zeroes. Data sheet: 7447 -Follow link for pin-out and logic symbol.

Review: Asynchronous versus Synchronous Counters 4-bit Asynchronous Counter (also called ripple counter): 4-bit Synchronous Counter: 20

Synchronous Counters In a synchronous counter all flip-flops are clocked together with a common clock pulse. Synchronous counters overcome the disadvantage of accumulated propagation delays, but generally they require more circuitry to control states changes. This 3-bit binary synchronous counter has the same count sequence as the 3-bit asynchronous counter shown previously. HIGH Q0 Q0Q1 Q0 Q1 Q2 J0 J1 J2 C C C K0 K1 K2 CLK

A 4-bit Synchronous Binary Counter The 74LS163 is a 4-bit IC synchronous counter with additional features over a basic counter. It has parallel load, a CLR input, two count enables, and a ripple count output that signals when the count has reached the terminal count. Data inputs D0 D1 D2 D3 CLR LOAD ENT RCO ENP CLK Example waveforms are on the next slide… Q0 Q1 Q2 Q3 Data outputs

Data inputs Data outputs CLR LOAD D0 D1 D2 D3 CLK ENP ENT Q0 Q1 Q2 Q3 RCO 12 13 14 15 0 1 2 Count Inhibit Clear Preset

A Family of Four-Bit Synchronous Counter ICs 74160 and 74162: Four-bit synchronous decade counters (MOD 10) These two are the same as each other except that 74160 has asynchronous clear, while 74162 has synchronous clear. 74161 and 74163: Four-bit synchronous binary counters (MOD 16) These two are the same as each other except that 74161 has asynchronous clear, while 74163 has synchronous clear. -LOAD is synchronous on all. -Do Practice Question 5. -Datasheet incorrectly shows clock as negative edge-triggered on ‘160, ‘161, ‘162, and ‘163, but correctly shows it as positive edge-triggered on LS versions.

Up/Down Synchronous Counters Data inputs Data outputs MAX/MIN CLK Q0 Q1 Q2 Q3 LOAD CTEN RCO D/U D0 D1 D2 D3 C CTR DIV 10 74HC190 The 74HC190 is a high speed CMOS synchronous up/down decade (MOD-10) counter with parallel load capability. It also has a active LOW ripple clock output (RCO) and a MAX/MIN output when the terminal count is reached. Data inputs Data outputs MAX/MIN CLK Q0 Q1 Q2 Q3 LOAD CTEN RCO D/U D0 D1 D2 D3 C CTR DIV 16 74HC191 The 74HC191 has the same inputs and outputs but is a synchronous up/down binary (MOD-16) counter.

A Family of Four-Bit Up/Down Synchronous Counter ICs 74190 Four-bit up/down decade counter (MOD 10) 74191 Four-bit up/down binary counter (MOD 16) -Note that LOAD is asynchronous. -Do Practice Question 6.

Cascading Counters Most counter chips are 4-bit counters, with a modulus of 16 or less. To get larger moduli, you cascade two or more counter chips together. When you cascade counters, their moduli multiply, not add. Example: If you cascade a MOD-10 counter with a MOD-16 counter, you get a MOD-160 counter. The connections for cascading counters differ depending on whether you’re using asynchronous counters or synchronous counters. 27

Cascading asynchronous counters -What MOD is this counter? 28

Cascading Synchronous Counters For cascading, most synchronous counter chips have one or more enable input pins and one or more terminal-count output pins. General idea: one chip’s terminal-count output drives the next chip’s enable input. (See next slide). These pins go by various names such as : CTEN, CEN, ENT, ENP, G for the enable inputs TC, CO, RCO, MAX, MAX/MIN for the terminal- count outputs. Also, depending on the chip, these pins may be active-high or active-low, so you may need to insert an inverter. 29

Example Solution Cascading synchronous counters For synchronous IC counters, the next counter is enabled only when the terminal count of the previous stage is reached. HIGH CLK Q0 Q1 Q2 C Counter 1 Counter 2 CTEN CTR DIV 16 Q3 TC fin fout Explain operation. Some variations to this basic idea: -May have more than one enable (‘160). -Alternate names for enable (ENT, ENP) and TC (RCO, CO, BO) pins. -Enable and/or TC pins may be active low instead of active-high. What is the modulus of these cascaded counters? If fin =100 kHz, what is fout? Example Solution a) Each counter divides the frequency by 16. Thus the modulus is 162 = 256. b) The output frequency is 100 kHz/256 = 391 Hz 30