1. Counters

2. November 5, 2003 Introduction: Counters  Counters are circuits that cycle through a specified number of states.  Two types of counters:  synchronous (parallel) counters  asynchronous (ripple) counters  Ripple counters allow some flip-flop outputs to be used as a source of clock for other flip-flops.  Synchronous counters apply the same clock to all flip-flops. CS1104-13 Introduction: Counters 2

3. November 5, 2003 Asynchronous (Ripple) Counters  Asynchronous counters: the flip-flops do not change states at exactly the same time as they do not have a common clock pulse.  Also known as ripple counters, as the input clock pulse “ripples” through the counter – cumulative delay is a drawback.  n flip-flops  a MOD (modulus) 2 n counter. (Note: A MOD-x counter cycles through x states.)  Output of the last flip-flop (MSB) divides the input clock frequency by the MOD number of the counter, hence a counter is also a frequency divider. CS1104-13 Asynchronous (Ripple) Counters 3

4. November 5, 2003 Asynchronous (Ripple) Counters  Example: 2-bit ripple binary counter.  Output of one flip-flop is connected to the clock input of the next more-significant flip-flop. CS1104-13 Asynchronous (Ripple) Counters 4 K J K J HIGH Q0Q0 Q1Q1 Q0Q0 FF1 FF0 CLK CC Timing diagram 00  01  10  11  00... 4321CLK Q0Q0 Q0Q0 Q1Q1 11 11 0 00 00 0

5. November 5, 2003 Asynchronous (Ripple) Counters  Example: 3-bit ripple binary counter. CS1104-13 Asynchronous (Ripple) Counters 5 K J K J Q0Q0 Q1Q1 Q0Q0 FF1 FF0 CC K J Q1Q1 C FF2 Q2Q2 CLK HIGH

6. November 5, 2003 Asynchronous (Ripple) Counters  Propagation delays in an asynchronous (ripple-clocked) binary counter.  If the accumulated delay is greater than the clock pulse, some counter states may be misrepresented! CS1104-13 Asynchronous (Ripple) Counters 6 4321CLK Q0Q0 Q1Q1 Q2Q2 t PLH (CLK to Q 0 ) t PHL (CLK to Q 0 ) t PLH (Q 0 to Q 1 ) t PHL (CLK to Q 0 ) t PHL (Q 0 to Q 1 ) t PLH (Q 1 to Q 2 )

7. November 5, 2003 Asynchronous (Ripple) Counters  Example: 4-bit ripple binary counter (negative-edge triggered). CS1104-13 Asynchronous (Ripple) Counters 7 K J K J Q1Q1 Q0Q0 FF1FF0 CC K J C FF2 Q2Q2 CLK HIGH K J C FF3 Q3Q3

8. November 5, 2003 Asyn. Counters with MOD no. < 2 n  States may be skipped resulting in a truncated sequence.  Technique: force counter to recycle before going through all of the states in the binary sequence.  Example: Given the following circuit, determine the counting sequence (and hence the modulus no.) CS1104-13 Asynchronous Counters with MOD number < 2^n 8 K JQ Q CLK CLR K JQ Q CLK CLR K JQ Q CLK CLR CBA BCBC All J, K inputs are 1 (HIGH).

9. November 5, 2003 Asyn. Counters with MOD no. < 2 n  Example (cont’d): CS1104-13 Asynchronous Counters with MOD number < 2^n 9 K JQ Q CLK CLR K JQ Q CLK CLR K JQ Q CLK CLR CBA BCBC All J, K inputs are 1 (HIGH). MOD-6 counter produced by clearing (a MOD-8 binary counter) when count of six (110) occurs.

10. November 5, 2003 Asyn. Counters with MOD no. < 2 n  Example (cont’d): Counting sequence of circuit (in CBA order). CS1104-13 Asynchronous Counters with MOD number < 2^n 10 11 1 00 0 00 1 11 0 10 1 10 0 01 0 01 1 Temporary state Counter is a MOD-6 counter. 000000 100100 010010 110110 001001 101101 000000 100100

11. November 5, 2003 Asyn. Counters with MOD no. < 2 n  Exercise: How to construct an asynchronous MOD-5 counter? MOD-7 counter? MOD-12 counter?  Question: The following is a MOD-? counter? CS1104-13 Asynchronous Counters with MOD number < 2^n 11 K JQ Q CLR CBA CDEFCDEF All J = K = 1. K JQ Q CLR K JQ Q K JQ Q K JQ Q K JQ Q DEF

12. November 5, 2003 Asyn. Counters with MOD no. < 2 n  Decade counters (or BCD counters) are counters with 10 states (modulus-10) in their sequence. They are commonly used in daily life (e.g.: utility meters, odometers, etc.).  Design an asynchronous decade counter. CS1104-13 Asynchronous Counters with MOD number < 2^n 12 D CLK HIGH K J C CLR Q K J C Q C K J C Q B K J C Q A (A.C)'

13. November 5, 2003 Asyn. Counters with MOD no. < 2 n  Asynchronous decade/BCD counter (cont’d). CS1104-13 Asynchronous Counters with MOD number < 2^n 13 D CLK HIGH K J C CLR Q K J C Q C K J C Q B K J C Q A (A.C)' 00000000 10001000 01000100 11001100 00100010 10101010 01100110 11101110 00010001 10011001 00000000

14. November 5, 2003 Asynchronous Down Counters  So far we are dealing with up counters. Down counters, on the other hand, count downward from a maximum value to zero, and repeat.  Example: A 3-bit binary (MOD-2 3 ) down counter. CS1104-13 Asynchronous Down Counters 14 K J K J Q1Q1 Q0Q0 C C K J C Q2Q2 CLK 1 Q Q' Q Q Q 3-bit binary up counter 3-bit binary down counter 1 K J K J Q1Q1 Q0Q0 C C K J C Q2Q2 CLK Q Q' Q Q Q

15. November 5, 2003 Asynchronous Down Counters  Example: A 3-bit binary (MOD-8) down counter. CS1104-13 Asynchronous Down Counters 15 00 1 00 0 11 1 01 0 01 1 10 0 11 0 10 1 1 K J K J Q1Q1 Q0Q0 C C K J C Q2Q2 CLK Q Q' Q Q Q

16. November 5, 2003 Cascading Asynchronous Counters  Larger asynchronous (ripple) counter can be constructed by cascading smaller ripple counters.  Connect last-stage output of one counter to the clock input of next counter so as to achieve higher-modulus operation.  Example: A modulus-32 ripple counter constructed from a modulus-4 counter and a modulus-8 counter. CS1104-13 Cascading Asynchronous Counters 16 K J K J Q1Q1 Q0Q0 C C CLK Q Q' Q Q K J K J Q3Q3 Q2Q2 C C K J C Q4Q4 Q Q Q Q Modulus-4 counterModulus-8 counter

17. November 5, 2003 Cascading Asynchronous Counters  Example: A 6-bit binary counter (counts from 0 to 63) constructed from two 3-bit counters. CS1104-13 Cascading Asynchronous Counters 17 3-bit binary counter 3-bit binary counter Count pulse A 0 A 1 A 2 A 3 A 4 A 5

18. November 5, 2003 Cascading Asynchronous Counters  If counter is a not a binary counter, requires additional output.  Example: A modulus-100 counter using two decade counters. CS1104-13 Cascading Asynchronous Counters 18 CL K Decade counter Q 3 Q 2 Q 1 Q 0 C CTE N TC 1 Decade counter Q 3 Q 2 Q 1 Q 0 C CTE N TC fre q freq/1 0 freq/10 0 TC = 1 when counter recycles to 0000

19. November 5, 2003 Synchronous (Parallel) Counters  Synchronous (parallel) counters: the flip-flops are clocked at the same time by a common clock pulse.  We can design these counters using the sequential logic design process (covered in Lecture #12).  Example: 2-bit synchronous binary counter (using T flip-flops, or JK flip-flops with identical J,K inputs). CS1104-13 Synchronous (Parallel) Counters 19 0100 1011

20. November 5, 2003 Synchronous (Parallel) Counters  Example: 2-bit synchronous binary counter (using T flip-flops, or JK flip-flops with identical J,K inputs). CS1104-13 Synchronous (Parallel) Counters 20 TA 1 = A 0 TA 0 = 1 1 K J K J A1A1 A0A0 C C CLK Q Q' Q Q

21. November 5, 2003 Synchronous (Parallel) Counters  Example: 3-bit synchronous binary counter (using T flip-flops, or JK flip-flops with identical J, K inputs). CS1104-13 Synchronous (Parallel) Counters 21 TA 2 = A 1.A 0 A2A2 A1A1 A0A0 1 1 TA 1 = A 0 TA 0 = 1 A2A2 A1A1 A0A0 1 11 1 A2A2 A1A1 A0A0 111 1111 1

22. November 5, 2003 Synchronous (Parallel) Counters  Example: 3-bit synchronous binary counter (cont’d). TA 2 = A 1.A 0 TA 1 = A 0 TA 0 = 1 CS1104-13 Synchronous (Parallel) Counters 22 1 A2A2 CP A1A1 A0A0 K Q JK Q JK Q J

23. November 5, 2003 Synchronous (Parallel) Counters  Note that in a binary counter, the n th bit (shown underlined) is always complemented whenever 011…11  100…00 or111…11  000…00  Hence, X n is complemented whenever X n-1 X n-2... X 1 X 0 = 11…11.  As a result, if T flip-flops are used, then TX n = X n-1. X n-2..... X 1. X 0 CS1104-13 Synchronous (Parallel) Counters 23

24. November 5, 2003 Synchronous (Parallel) Counters  Example: 4-bit synchronous binary counter. TA 3 = A 2. A 1. A 0 TA 2 = A 1. A 0 TA 1 = A 0 TA 0 = 1 CS1104-13 Synchronous (Parallel) Counters 24 1 K J K J A1A1 A0A0 C C CLK Q Q' Q Q K J A2A2 C Q K J A3A3 C Q A 1.A 0 A 2.A 1.A 0

25. November 5, 2003 Synchronous (Parallel) Counters  Example: Synchronous decade/BCD counter. CS1104-13 Synchronous (Parallel) Counters 25 T 0 = 1 T 1 = Q 3 '.Q 0 T 2 = Q 1.Q 0 T 3 = Q 2.Q 1.Q 0 + Q 3.Q 0

26. November 5, 2003 Synchronous (Parallel) Counters  Example: Synchronous decade/BCD counter (cont’d). CS1104-13 Synchronous (Parallel) Counters 26 T 0 = 1 T 1 = Q 3 '.Q 0 T 2 = Q 1.Q 0 T 3 = Q 2.Q 1.Q 0 + Q 3.Q 0 1 Q1Q1 Q0Q0 CLK T C Q Q' Q Q2Q2 Q3Q3 T C Q Q T C Q Q T C Q Q

27. November 5, 2003 Up/Down Synchronous Counters  Up/down synchronous counter: a bidirectional counter that is capable of counting either up or down.  An input (control) line Up/Down (or simply Up) specifies the direction of counting.  Up/Down = 1  Count upward  Up/Down = 0  Count downward CS1104-13 Up/Down Synchronous Counters 27

28. November 5, 2003 Up/Down Synchronous Counters  Example: A 3-bit up/down synchronous binary counter. CS1104-13 Up/Down Synchronous Counters 28 TQ 0 = 1 TQ 1 = (Q 0.Up) + (Q 0 '.Up' ) TQ 2 = ( Q 0.Q 1.Up ) + (Q 0 '. Q 1 '. Up' ) Up counter TQ 0 = 1 TQ 1 = Q 0 TQ 2 = Q 0.Q 1 Down counter TQ 0 = 1 TQ 1 = Q 0 ’ TQ 2 = Q 0 ’.Q 1 ’

29. November 5, 2003 Up/Down Synchronous Counters  Example: A 3-bit up/down synchronous binary counter (cont’d). CS1104-13 Up/Down Synchronous Counters 29 TQ 0 = 1 TQ 1 = (Q 0.Up) + (Q 0 '.Up' ) TQ 2 = ( Q 0.Q 1.Up ) + (Q 0 '. Q 1 '. Up' ) 1 Q1Q1 Q0Q0 CLK T C Q Q' Q T C Q Q T C Q Q Up Q2Q2

30. November 5, 2003 Designing Synchronous Counters  Covered in Lecture #12.  Example: A 3-bit Gray code counter (using JK flip-flops). CS1104-13 Designing Synchronous Counters 30 10 0 00 0 00 1 10 1 11 1 11 0 01 1 01 0

31. November 5, 2003 Designing Synchronous Counters  3-bit Gray code counter: flip-flop inputs. CS1104-13 Designing Synchronous Counters 31 0 10 1 00 01 11 10 Q2Q2 Q1Q0Q1Q0 XXXX 1 JQ 2 = Q 1.Q 0 ' 0 10 1 00 01 11 10 Q2Q2 Q1Q0Q1Q0 XXXX 1 KQ 2 = Q 1 '.Q 0 ' 0 10 1 00 01 11 10 Q2Q2 Q1Q0Q1Q0 XX XX1 JQ 1 = Q 2 '.Q 0 0 10 1 00 01 11 10 Q2Q2 Q1Q0Q1Q0 XX XX 1 KQ 1 = Q 2.Q 0 0 10 1 00 01 11 10 Q2Q2 Q1Q0Q1Q0 XX XX1 JQ 0 = Q 2.Q 1 + Q 2 '.Q 1 ' = (Q 2  Q 1 )' 1 0 10 1 00 01 11 10 Q2Q2 Q1Q0Q1Q0 XX XX1 1 KQ 0 = Q 2.Q 1 ' + Q 2 '.Q 1 = Q 2  Q 1

32. November 5, 2003 Designing Synchronous Counters  3-bit Gray code counter: logic diagram. JQ 2 = Q 1.Q 0 ' JQ 1 = Q 2 '.Q 0 JQ 0 = (Q 2  Q 1 )' KQ 2 = Q 1 '.Q 0 ' KQ 1 = Q 2.Q 0 KQ 0 = Q 2  Q 1 CS1104-13 Designing Synchronous Counters 32 Q1Q1 Q0Q0 CLK Q2Q2 J C Q Q' K J C Q K J C Q K Q2'Q2' Q0'Q0' Q1'Q1'

33. November 5, 2003 Shift Register Counters  Ring Counters  A ring counter is basically a circulating shift register in which the output of the most significant stage is fed back to the input of the least significant stage. The following is a 4-bit ring counter constructed from D flip-flops. The output of each stage is shifted into the next stage on the positive edge of a clock pulse. If the CLEAR signal is high, all the flip-flops except the first one FF0 are reset to 0. FF0 is preset to 1 instead.

34. November 5, 2003 Shift Register Counters  Since the count sequence has 4 distinct states, the counter can be considered as a mod-4 counter. Only 4 of the maximum 16 states are used, making ring counters very inefficient in terms of state usage. But the major advantage of a ring counter over a binary counter is that it is self-decoding. No extra decoding circuit is needed to determine what state the counter is in.

35. November 5, 2003 Shift Register Counters  Johnson Counters  Johnson counters are a variation of standard ring counters, with the inverted output of the last stage fed back to the input of the first stage. They are also known as twisted ring counters. An n-stage Johnson counter yields a count sequence of length 2n, so it may be considered to be a mod-2n counter. The circuit above shows a 4-bit Johnson counter. The state sequence for the counter is given in the table as well as the animation on the left.

36. November 5, 2003 Shift Register Counters  Again, the apparent disadvantage of this counter is that the maximum available states are not fully utilized. Only eight of the sixteen states are being used.  Beware that for both the Ring and the Johnson counter must initially be forced into a valid state in the count sequence because they operate on a subset of the available number of states. Otherwise, the ideal sequence will not be followed.