1. EGR 2131 Unit 10 Registers and Counters
Read Brown & Vranesic, Sections 7.8 to 7.13 and Sections A.10.6 to A.10.9.
Homework #10 and Lab #10 due next week.
Quiz next week.
-Handouts: Unit 9 quiz, Unit 10 practice sheet. Also bring Lab3Counter project on a flash drive for students who don’t have it.

2. A Brief Detour: Contact Bounce
Before looking at this unit’s main topics, the next nine slides discuss an equipment-related issue that we’ll have to deal with in the upcoming labs.
The issue, which is a very common practical problem that you should be able to recognize and address, is called contact bounce.
Contact bounce is not discussed in the textbook.

3. Contact Bounce
Although it’s not obvious to us in everyday life, most mechanical switches suffer from contact bounce.
When you flip the switch lever, the contacts inside the switch repeatedly bounce open and closed for a short time ( 50 ms).
This can lead to problems in digital circuits, particularly in circuits that keep track of how many times a switch was flipped.

4. Contact Bounce: An Illustration
You may recall that we ran into this problem in Lab 3.
Open your Quartus project named Lab3Counter, download it to the DE2-115 board, and note that when you press the KEY3 pushbutton, the count on the green LEDs often increases by more than one.

5. Ways to Solve Contact Bounce
There are several standard ways to debounce a switch.
In hardware, one standard solution uses a latch or flip-flop. Another uses an RC circuit with a Schmitt-trigger gate. (Good discussion at
Debouncing can also be done in software by checking the input at well-spaced time intervals, and only accepting a value if it is steady for some time.

6. Debounce Circuit on the DE2-115 Board?
The DE User Manual claims (on pages ) that the push-buttons are debounced with a Schmitt Trigger circuit.
But as we’ve seen, the push-buttons still bounce.
On the other hand, the red trainer’s pulse switches are properly debounced….

7. Debounce Circuit on Our Red Trainer’s Pulse Switches
The red trainer uses cross-coupled NAND gates to debounce the pulse switches.

8. Proper Debouncing: An Illustration
Modify Lab3Counter to use pin D9 (on the general-purpose I/O connector) instead of pin R24.
Then connect pin D9 to the red trainer’s pulse-switch A output. (Use another wire to establish common ground.)

9. A Better Solution
A page on Digi-Key’s website describes a debouncer circuit (and equivalent VHDL code) that you can build in Quartus.
We’ll be able to understand this circuit in another week or two. But for now, just download the .vhd and .bsf files from the course’s Unit 10 webpage, and insert the .bsf file into any schematic diagram that requires debouncing.

10. A Better Solution: Illustration
After downloading the files into a folder where you store your Quartus projects, modify Lab3Counter by changing pin D9 back to pin R24 and inserting the debounce .bsf as shown.
Note that the debouncer requires a 50 MHz clock to work properly.

11. Going Forward…
Many of the circuits that you’ll build in the coming weeks use a push-button to clock a circuit. You should get into the habit of inserting debounce.bsf into these circuits to debounce the clock, even if the written directions don’t tell you to do this.
Now, on to the main topics of this unit….

12. Registers
Recall that a latch or flop-flop stores one bit of information. When a set of n flip-flops that share a clock are used to store n bits of information, such as an n-bit number, we call these flip-flops a register.
The next slide shows a good application, which you’ll build in lab. It’s an adder with registered feedback that sequentially adds a list of numbers, one at a time.

13. Registers: An Application (Figure 7.42 from textbook)
4-bit register
Sequence of operation:
Reset the register.
Place a 4-bit number on the Data inputs.
Pulse the Clock. Then return to Step 2. At all times, the Sum outputs hold the running total of the numbers so far.
4-bit adder
-Do Practice Question 1.

14. Asynchronous versus Synchronous Inputs
When working with clocked circuits such as registers and counters, we must pay attention to whether specific inputs are synchronous or asynchronous.
For example, the register on the previous slide has an input labeled aclr, which stands for asynchronous clear. As soon as this input goes high, the register is cleared.

15. Asynchronous versus Synchronous Inputs (Cont’d.)
On the other hand, if that register had a synchronous clear input, then the register would not be cleared until the next active clock edge after the clear input goes high.
Both kinds are useful, and we’ll see examples of circuits that have one or the other.

16. Shift Registers
Many registers provide the additional ability to shift their contents to the left or right, resulting in what we call a shift register.
A common application of shift registers is conversion from serial format to parallel format, or vice versa.

17. Data Transfer: Serial versus Parallel
In general, data can be transmitted either serially (one bit at a time) or in parallel (many bits at a time).
Only one bit is transmitted per clock period.
Several bits are transmitted in a single clock period.
Do practice questions 2, 3.

18. Ports on a Typical Laptop Computer
RS-232 (Serial)
USB (Serial)
PS/2 Mouse (Serial)
IEEE 1394 (Serial)
Printer (Parallel)
VGA (Analog video)

19. Data Movement Within Shift Registers
Some typical data movements within shift registers are illustrated here.
Data in
Data in
Data out
Data out
Data in
Data out
-Not very glamorous, but important.
Serial in/shift right/serial out
Serial in/shift left/serial out
Parallel in/serial out
Data in
Data in
Data out
Data out
Serial in/parallel out
Parallel in/parallel out
Rotate right
Rotate left

20. Shift Register Applications
Data bus
A UART (Universal Asynchronous Receiver Transmitter) is a serial-to-parallel converter and a parallel to serial converter.
UARTs are commonly used in small systems where one device must communicate with another. Outgoing parallel data is converted to serial form, and incoming serial data is converted to parallel form.
CLK
CLK
Serial data out
Serial data in

21. Serial-in/Serial out Shift Register
Shift registers are available in IC form or can be constructed from discrete flip-flops, as shown here with a five-bit serial-in serial-out register.
Each clock pulse will move an input bit to the next flip-flop. For example, a 1 is shown as it moves across. 1 1 1 1 1 1
-Demo with Multisim file shiftReg.ms10.
CLK
CLK
CLK
CLK
CLK

22. A Basic Application
One application of shift registers is conversion of serial data to parallel form.
For example, assume the binary number 1011 is loaded sequentially, one bit at each clock pulse.
After 4 clock pulses, the data is available at the parallel output.
CLK
CLK
CLK
CLK

23. Some 74xx Shift Register Chips
74164 (8-bit serial in/parallel out)
Clear is asynchronous.
74165 (8-bit parallel in/serial out)
Parallel Load is asynchronous.
74194 (4-bit bidirectional universal)
Parallel Load is synchronous.
74195 (4-bit parallel access)

24. 74164 Shift Register
The is an 8-bit serial in/parallel out shift register.
One of the two serial data inputs may be used as an active-HIGH enable to gate the other input. If no enable is needed, the other serial input can be connected to VCC.
Data is entered on the rising edge of the clock.
The has an active LOW asynchronous clear.

25. 74164 Shift Register: Sample Waveforms
-Do Practice Question 4.

26. 74194 Universal Shift Register
The is a 4-bit bidirectional universal shift register, having both serial and parallel input and output capability.
See next slide for sample waveforms….
S1 S0 Mode
Hold
Shift right
Shift left
Parallel load (synchronous)

27. 74194 Shift Register: Sample Waveforms
-Do Practice Question 5.

28. Example Solution Another Shift Register Application: Time Delay
Shift registers can be used to delay a digital signal by a predetermined amount.
An 8-bit serial in/serial out shift register has a 40 MHz clock. What is the total delay through the register?
Example
Solution
The delay for each clock is 1/40 MHz = 25 ns
-Do as Practice Question 6.
25 ns
The total delay is 8 x 25 ns = 200 ns
= 200 ns

29. Registers and Shift Registers in Quartus
As you might expect, Quartus gives you several ways to implement registers and shift registers:
Using schematic capture:
Build registers out of individual flip-flops.
Place virtual copies of 74xx chips such as the or
Place and configure customizable components from Quartus’ Library of Parameterized Modules:
lpm_ff for registers.
lpm_shiftreg for shift registers.
Using VHDL code.

30. Counting in Binary
As you know, the binary count sequence follows a familiar pattern of 0’s and 1’s as described in Section 2-2 of the text.
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
LSB changes on every number.
The next bit changes on every other number.
The next bit changes on every fourth number.

31. Counting in Binary
A counter can form the same pattern of 0’s and 1’s with logic levels. The first stage in the counter represents the least significant bit – notice that these waveforms follow the same pattern as counting in binary.
LSB
-How does a single JK flip-flop in toggle mode behave? It’s a MOD-2 counter (or divide-by 2 counter) that counts from 0 to 1 and then recycles.
-Basic idea for higher-MOD counters is to connect several flip-flops together in such a way that they count up from 0 to some terminal state, at which point they recycle back to 0.
-Two main ways to do this: asynchronous (ripple) counters and synchronous counters, both with many variations. Preview by drawing two-bit counters, and do Practice Questions 7, 8.
MSB

32. Synchronous versus Asynchronous
The synchronous/asynchronous distinction has different meanings:
As applied to inputs: A change on a synchronous input doesn’t affect the outputs until the next active clock edge, but a change on an asynchronous input affects the outputs immediately. 32

33. Synchronous versus Asynchronous
The synchronous/asynchronous distinction has different meanings:
As applied to counters: in a synchronous counter, the outputs can all change at the same instant; but in an asynchronous counter, there’s a brief delay between the changing of the outputs. 33

34. Three-Bit Asynchronous Counter
In an asynchronous counter, the clock is applied only to the first stage. Each subsequent stage gets its clock from the previous stage.
The asynchronous counter shown is a three-bit counter (also called MOD-8 counter or divide-by-8 counter).
Note these are positive-edge-triggered flip-flops, that’s why clocks are driven from Q’ output. 34

35. Terminology: Modulus and Divide-By
As noted on the previous slide, the three-bit counter shown here is also called a MOD-8 counter or a divide-by-8 counter.
A counter’s modulus is the number of different values it can count through. The example shown has a modulus of 8. (The eight values are 000 through 111.)
Also, the signal at Q2 will have a frequency equal to one-eighth of the incoming clock frequency. That’s why we can call it a divide-by-8 counter. 35

36. Three-Bit Asynchronous Counter: Waveforms
Asynchronous counters are sometimes called ripple counters, because the stages do not all change together. This can be a major drawback.
Notice how delays are cumulative as each stage in a counter is clocked later than the previous stage.
CLK Q0 Q1 Q2
Q0 is delayed by 1 propagation delay, Q1 by 2 delays and Q2 by 3 delays.

37. The 74LS93 Asynchronous Counter
The 74LS93 has one independent toggle J-K flip-flop driven by CLK A and three toggle J-K flip-flops that form an asynchronous counter driven by CLK B.
The counter can be extended to form a 4-bit counter by connecting Q0 to the CLK B input. Two inputs are provided that clear the count.
CLK B J0 J1 J2 J3
CLK A C C C C
We’ve used this chip in Labs 1, 2, and 8. K0 K1 K2 K3
All J and K inputs are connected internally HIGH
RO (1)
RO (2) Q0 Q1 Q2 Q3

38. Some 74XX Asynchronous Counter ICs
7490 Four bit decade counter (MOD 10)
7492 Four bit divide-by-12 counter (MOD 12)
7493 Four bit binary counter (MOD 16)
Do Practice Questions 9, 10.

39. Asynchronous Decade Counter
This counter uses a NAND gate to recycle the count sequence to zero after the 1001 state, resulting in a MOD-10 counter (or decade counter). Other truncated sequences can be obtained using a similar technique.
CLR
CLK K0 J0 Q0 C J1 J2 K1 K2 Q1 Q2
HIGH J3 K3 Q3
-Variation on the basic counter, except extra gates force the count back to 0 before it gets all the way up to 15. This is called a truncated sequence.
Waveforms are on the following slide…

40. Asynchronous versus Synchronous Counters
3-bit Asynchronous Counter (also called ripple counter):
3-bit Synchronous Counter: 40

41. Synchronous Counters
In a synchronous counter all flip-flops are clocked together with a common clock signal. Synchronous counters overcome the disadvantage of accumulated propagation delays, but generally they require more circuitry to control states changes.

42. Some 74XX Synchronous Counter ICs
74160 and 74162: Four-bit synchronous decade counters (MOD 10)
These two are the same as each other except that has asynchronous clear, while has synchronous clear.
In both, LOAD is synchronous and active-low.
74161 and 74163: Four bit synchronous binary counters (MOD 16)
These two are the same as each other except that has asynchronous clear, while has synchronous clear.
-Datasheet incorrectly shows clock as negative edge-triggered on ‘160, ‘161, ‘162, and ‘163, but correctly shows it as positive edge-triggered on LS versions.

43. 74163: A 4-bit Synchronous Binary Counter
The 74LS163 is a 4-bit synchronous counter with additional features over a basic counter: parallel load, a CLR input, two count enables, and a ripple count output that signals when the count has reached its maximum value.
See example waveforms on next slide…

44. 74163 Example Waveforms
-Do Practice Question 11.

45. Some 74XX Up/Down Synchronous Counter ICs
74190 Four bit up/down decade counter (MOD 10)
74191 Four bit up/down binary counter (MOD 16)
In both, LOAD is asynchronous and active-low.

46. 74190: A 4-bit Synchronous Up/Down Decade Counter
The 74LS190 is a synchronous up/down decade (MOD-10) counter with parallel-load. It has an active-LOW ripple carry output (RCO) and a MAX/MIN output that indicates when the terminal count is reached.
-Do Practice Question 12.

47. Counters in Quartus
As you might expect, Quartus gives you several ways to implement counters:
Using schematic capture:
Build counters out of individual flip-flops.
Place virtual copies of 74xx chips such as the 7490 or
Place and configure a customizable counter (named lpm_counter) from Quartus’ Library of Parameterized Modules.
Using VHDL code.

48. Shift Counters
Shift registers are often used to form counter-like circuits, called shift counters, that recirculate a pattern of 0’s and 1’s.
Two common examples are the ring counter and the Johnson counter.

49. Ring Counter
The ring counter can be implemented with either D flip-flops or J-K flip-flops.
Here is a 4-bit ring shift counter constructed from a series of D flip-flops. Notice the feedback.
It can also be implemented with J-K flip flops.

50. Ring Counter
Redrawing the ring counter (without the clock shown) shows why it is a “ring”.
In practical applications, the counter is preloaded with the desired pattern (usually a single 0 or 1).
It has n states, where n = number of flip-flops.

51. Ring Counter
A common pattern for a ring counter is to load it with a single 1 or a single 0. The waveforms shown here are for an 8-bit ring counter with a single 1.
-Do Practice Question 13.
-Demo with Multisim file shiftCounter.ms10.

52. Johnson Counter The Johnson counter can be made with D flip-flops…
… or with J-K flip flops. Here Q3 and Q3 are fed back to the J and K inputs with a “twist”.

53. Johnson Counter
Redrawing the same Johnson counter (without the clock shown) illustrates why it is sometimes called as a “twisted-ring” counter.
“twist”
-Demo by modifying Multisim to change from ring counter to Johnson counter.

54. Question Johnson Counter
The Johnson counter is useful when you need a sequence that changes by only one bit at a time but it has a limited number of states (2n, where n = number of stages).
The first five counts for a 4-bit Johnson counter that is initially cleared are: CLK Q0 Q1 Q2 Q3 1 2 3 4 5 6 7
-Do Practice Question 14.
Question
What are the remaining 3 states?

55. Keyboard Encoder
The keyboard encoder is an example of where a ring counter is used in a small system to encode a key press.
Two shift registers are connected as an 8-bit ring counter preloaded with a single 0. As the 0 circulates in the ring counter, it “scans” the keyboard looking for any row that has a key closure. When one is found, a corresponding column line is connected to that row line. The combination of the unique column and row lines identifies the key. The schematic is shown on the following slide…

56. 8-bit ring counter (two cascaded 74195s)
74147s used as keyboard encoders (similar to example from Unit 8 slides)
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