SERENA Progress Santa Fe, May 14 th 2008 AMDL - Andrea M. Di Lellis SERENA Project: the kick off

SERENA Progress Santa Fe, May 14 th 2008 AMDL - Andrea M. Di Lellis SERENA Current schedule

SERENA Progress Santa Fe, May 14 th 2008 AMDL - Andrea M. Di Lellis SERENA LONG TERM PLAN

SERENA Progress Santa Fe, May 14 th 2008 AMDL - Andrea M. Di Lellis SERENA DOCUMENTATION (see Released_doc annex)

SERENA Progress Santa Fe, May 14 th 2008 AMDL - Andrea M. Di Lellis SERENA SYSTEM AIV (see AIV_program_0.3 annex)

SERENA Progress Santa Fe, May 14 th 2008 AMDL - Andrea M. Di Lellis Outlook SERENA SCU / SYSTEM I/Fs developing status DHSU Architecture System Budgets

SERENA Progress Santa Fe, May 14 th 2008 AMDL - Andrea M. Di Lellis S pW 10 / (50) Mb/s LVDS Link 2Mb/s RS-422 Link Unit 5 NPA-IS SCU Electronics Unit- 1 (ELENA box (ELENA box) STROFIO 20° 20° FOV NPA-IS System S/C Spacewire SERENA Bus S/C fixation platforms S/C OBDH Unit 3/4 ELENA / MIPA 1.8° x 76°/ 9°x 180° Unit 2 PICAM 90°x 360° Redu SpW Bus SCU Limited PWR Bus 28 V DC SCU Limited Power Bus 28 V DC Main S/C Power Bus +28V DC Redu S/C Power Bus +28 V DC SCU L. PWR +28V DC SERENA SCU / SYSTEM

SERENA Progress Santa Fe, May 14 th 2008 AMDL - Andrea M. Di Lellis SERENA SCU / SYSTEM I/Fs

SERENA Progress Santa Fe, May 14 th 2008 AMDL - Andrea M. Di Lellis DHSU Block Diagram 3-EEPROM Leon-3 FT core courtesy By Gaisler Research TM Reset Circuitry SURVPROM8kx16SURVPROM8kx16 ACTEL RTAX2000S [A0..A16] [D0..D24] 2-SRAM512kx8 with EDAC 2-SRAM512kx8 2-EEPROM EEPROM Power Switch Transceiver 3-CubeCompressor3-CubeCompressor 3-Cube Power Switch Transceiver SPACEWIREkernel ECSS-E ASPACEWIREkernel TM/TC LVDS Transceivers S/C SPACEWIRE TC/TM I/F BP-MPO DHSU DPU, AMD - V1.0 Rev. C 3-SRAM512kx8 with EDAC 3-SRAM512kx8 1-EEPROM128kx8 1-EEPROM128kx8 EDAC 2x12 to16 Recon- structor 1-SRAM512kx8 with EDAC 1-SRAM512kx8 STROFIOI/FSTROFIOI/F POWER Control I/F POWER PWR EN/DIS LINEs ELENAI/FELENAI/F MIPAI/FMIPAI/F Developing & Testing I/F EMC FILTER +3.3V DC / DC Converter 50 MHz OSC S/C POWER I/F EMC FILTER PICAMI/FPICAMI/F LocTM/LocTC Serial 2Mb/s I/F Drivers LocTM/LocTC Serial 2Mb/s I/F Drivers LocTM/LocTC Serial 2Mb/s I/F Drivers LocTM/LocTC Serial SpW I/F Drivers

SERENA Progress Santa Fe, May 14 th 2008 AMDL - Andrea M. Di Lellis AHB Controller Memory Controller To SRAM I/F TO EEPROM I/F AHB/APB Bridge Timers UARTs IrqCtrl I/O Ports LEON CORE AHB Interface AMBA AHB AMBA APB APB/Switch Bridge CFG Port Main S/C SpW IF Redu S/C SpW IF To COMPR I/F SERENA I/Fs architecture SCU SpW I/F ELE Ser IF MIP Ser IF STR Ser IF Legend: 2Mb/s I/F PIC SpW IF

SERENA Progress Santa Fe, May 14 th 2008 AMDL - Andrea M. Di Lellis SERENA Grounding scheme

SERENA Progress Santa Fe, May 14 th 2008 AMDL - Andrea M. Di Lellis DATA HANDLING: Main DPUs inheritance FORMER AMDLs related experiences: CLUSTER CIS-2: DPU Designing & On-Board S/W (MAS281) DARA-NASA EQUATOR-S ESIC: On-Board S/W (MAS281) DMARS-96 &ESA MARS EXPRESS PFS: FFT DPU Design & On- Board S/W (AD21000) DOUBLE STAR HIA: Composition Experiment OnBoard S/W (MAS281) ESA SMART-1 AMIE: Microcamera - Power supply & S/C I/F board NASA/JPL DAWN: VIR On board compression S/W & GSE CURRENT AMDLs related experiences: ESA BEPICOLOMBO SERENA: PM and Design Manager ESA EXOMARS IRAS: Electronics Design Manager

SERENA Progress Santa Fe, May 14 th 2008 AMDL - Andrea M. Di Lellis Full representativeSCU board 100% mastered SCU H/W demonstration mdel DHSU Developing

SERENA Progress Santa Fe, May 14 th 2008 AMDL - Andrea M. Di Lellis SERENA ELE/SCU CPPA

SERENA Progress Santa Fe, May 14 th 2008 AMDL - Andrea M. Di Lellis SCU SENSORS I/Fs: MIPA #1/2

SERENA Progress Santa Fe, May 14 th 2008 AMDL - Andrea M. Di Lellis SCU SENSORS I/Fs: MIPA #2/2

SERENA Progress Santa Fe, May 14 th 2008 AMDL - Andrea M. Di Lellis SCU SENSORS I/Fs: ELE-STROFIO #1/2

SERENA Progress Santa Fe, May 14 th 2008 AMDL - Andrea M. Di Lellis SCU SENSORS I/Fs: ELE-STROFIO #2/2

SERENA Progress Santa Fe, May 14 th 2008 AMDL - Andrea M. Di Lellis SENSORS I/F implementation: e.g.MIPA

SERENA Progress Santa Fe, May 14 th 2008 AMDL - Andrea M. Di Lellis SpW Testing Configuration SCU SIM: PENDERs GR-XC3S FPGA based LEON3 LVDS I/F PICAM & S/C SIM I/F & HOST USB I/F

SERENA Progress Santa Fe, May 14 th 2008 AMDL - Andrea M. Di Lellis DHSU description The DHSU unit consists of the following functional blocks housed on a 100x160mm 2 Eurocard board: - Hi Rel FPGA based Control Unit ( Leon3 FT) -Hi Rel SRAM 512x2 kB EDAC Protected - HI Rel local power converter and power distribution switches - Rad Tolerant EEPROM 128x2 kB EDAC Protected Optionally on a second 100x100 mm 2 mezzanine board: - Rad Tolerant 200 MIPS DSP Based DPU Compressor and glue logic Main DHSU tasks are: - To receive and to distribute command to Sub-sys - to acquire data from active Sub-Sys - to download science and H/K data through the S/C interface ; - to control and manages the IRAS suite functions - to control and distributes primary power to Sub-Sys

SERENA Progress Santa Fe, May 14 th 2008 AMDL - Andrea M. Di Lellis EDAC Faulty Case: corrupted bus: - Above: 1 err detected & recovered - Bottom: 2 err detected

SERENA Progress Santa Fe, May 14 th 2008 AMDL - Andrea M. Di Lellis DHSU: LEON 3 H/W STATUS: Updating developing configuration of PENDERs GR-XC3S-1500 FPGA based LEON3 development/prototyping board XCONFIG & XGRLIB and uploading procedures via IMPACT tool (Xilinx) tested and running for customized Leon3 configuration. For ACTEL developing procured A3PE3000 complete developing platform Boot PROMs prepared. Received directly from Gaisler a customized.MCS version which encloses the optional GR SpW core. S/W STATUS: Updating S/W Development tools GRMON, GRSIM, BCC, GDB/DDD integrated on Cygwin and Win XP platforms. S/W development controlled under ECLIPSE 3.2. DOC Status Preliminary definition of the internal I/Fs to Sub-Subsystem communication protocol issued. Provided a 2nd issue of Communication Interface Control Document BC-SRN _.Doc OPEN ISSUES: no major issues

SERENA Progress Santa Fe, May 14 th 2008 AMDL - Andrea M. Di Lellis BUDGETS Power Mass TC Budget refined according to BC-SRN Communication Interface Control Document TM BUDGETS Ref BC-EST-RS Draft 2