1. Double Star meeting ESTEC 25/26 March 2002

2. Hardware Status Engineering breadboard fabricated to validate the FPGA concept – Using an ACTEL A1280 – Tested on the EM New Engineering breadboard under fabrication – Using a A54SX16 – Containing all the "cluster " like interfaces including FGM – Redundant Interface added (TM, TC, SPIN CLK) New connector (J04 – 25 pins) added close to J01 – 25 pins – For redundant interfaces

3. Double Star meeting 25/03/2002 ESTEC Engineering board

4. Double Star meeting ESTEC 25/26 March 2002 Software Status Documentation given to Andrea Maria Di Lellis First version received but not tested Development will continue in parallel with the hardware development

5. Double Star meeting 25/26 March 2002 US components status

6. Double Star meeting ESTEC 25/26 March 2002 Properties Interface board changed - equivalent size (see EID-B) Mass : 3.5 Kg (including radiation shielding) Power : 3.8 W max ; 2.8 W min (nominal)

7. Double Star meeting ESTEC 25/26 March 2002 Planning EM interface board : end March 2002 FM interface board : October 2002 EEPROM Software modification : end April 2002 PROM Software modification : end September 2002 FM integration : end November Verification under vacuum : ended by 20/12/2002 Environmental tests : 2 weeks Delivery : end January 2003

8. Double Star meeting ESTEC 25/26 March 2002 Standard Connectors sent to China : 14 February 2002 Documentation Status : Interface data sheet : 15 February 2002 Pin assignment and wire type : 15 February 2002 Control Files : 05 March 2002 On board monitoring : 20 March 2002

9. Double Star meeting ESTEC 25/26 March 2002 Outstanding Issues Thermal blanket fabrication Harness Interface test configuration Data collection during interface test Funding problem