1. Data handling, timing and power distribution scheme
Xiangyang Wenxy (IHEP)

2. SFA/PFA DHU-F Configurations
9 SFC and 4 PFC have the same external electrical interfaces,
The DHU-F to SFC/PFC interfaces are identical and interchangeable, So can be connected to any SFC/PFC.

3. DHU-F Main Functions TM handling TC handling(1553B)
Receives the data from the SFC/PFC, formats this data for telemetry.
Whether the science data is compressed depends on the telemetry capability which is still under discussion .
TC handling(1553B)
Receives commands from 1553B, processes and sends to SFC/PFC.
Receives housekeeping data from SFC/PFC, gathers his own housekeeping data, and sends to the spacecraft.
PPS and high accuracy clock distribution
Power distribution

4. Platform Electrical Interface
Power
Primary power,42V
Relay control lines to turn on or off DHU-F
1553B
Command Injection
Housekeeping
Science Data Interface
SPI-like interface
PPS & atomic clock
Analog housekeeping(some key currents and voltages)

5. Science Data Interface
Gate
Payload
Data
9 SFA
19.8
4 PFA
54.3
3SFA + 1PFA
20.2
Clk
Data
Synchronous serial communication interface used on HXMT;
Unidirectional，from payload to spacecraft,LVDS；
Three logic signals:
Gate：low active，pulse width equals to the length of the whole packet ；
Clk：Exists always，Spacecraft samples the data signal on the falling edge, Time between data signal changing and the clock risng edge ≤±10ns，duty cycle 45%~55%；
Data：Serial,MSB first.
clock rates:
HXMT: 8MHz
eXTP: 40MHz,Date 20.2Mbps

6. SFC/PFC Electrical Interface
Power:
Primary power,42V
Control Relay to turn on or off
High Speed Data Link(LVDS)
Sending Science data and engineering data to DHU-F
Low Speed Data Link(LVDS)
Sending housekeeping data to DHU-F
Receiving command from DHU-F
Analog housekeeping
A few of key currents and voltages
PPS and high accuracy clock distribution

7. High Speed Data Link Unidirectional,from SFC/PFC to DHU,LVDS;
Payload
Data
SFA
2.2
PFA
13.6
Unidirectional,from SFC/PFC to DHU,LVDS;
CLK: 20MHz
Data: The idle, no data state is high-voltage, Each packet is sent as a logic low start bit, a configurable number of data bits.

8. Low Speed Data Link
full duplex
RS232 protocol

9. Electrical Schematic Diagram
Cold redundant

10. Software
The FPGA take charge of science and engineering processing, MCU is not involved.
The MCU take charge of the other things:1553B command handling，Relay control，HK collecting,…

11. Candidates for MCU and FPGA
MCU：ATmegaS128
Similar to 51 interfaces
TID 30 Krad (Si)
SEL LET > 62.5Mev
128K Flash
4K RAM
4K EEPROM
FPGA
Anti-fuse：not in-system programmable
FLASH or SRAM，preferred， depend on the availability

12. Summary
This preliminary design is based on the HXMT satellite electrical interfaces, will be improved according to new functional and performance requirements.
The science data interface between the DHU-F and the satellite and SFA/PFA can be changed to spacewire if requested.