1. High Speed Digital Design Project SpaceWire Router By: Asaf Bercovich & Oren Cohen Advisor: Mony Orbach Semester: Winter 2007/2008 2-Semester Project Date: October 2008 Part A Final Presentation

2. Project Goal Designing a SpaceWire Switch Core (Router) compatible to ECSS-E-50-12A Standard. The design will be coded and simulated using Xilinx development enviroment and implemented onto a Xilinx VirtexII-Pro FPGA. Designing a SpaceWire Switch Core (Router) compatible to ECSS-E-50-12A Standard. The design will be coded and simulated using Xilinx development enviroment and implemented onto a Xilinx VirtexII-Pro FPGA.

3. System Topology Router

4. System Topology Router PORT Full duplex Low latency Point-to-point Wormhole Routing Asynchronous communication Automatic failover 400 Mb/s of Traffic Total

5. Layer 2 (Character Level) Network Port Receiver D1117 SpaceWire Port Architecture Port Controller Din Sin Dout Sout Sys Clock Reset RX DATA / Control TX DATA / Control Link Start State Machine Transmitter FIFO RX CLOCK FIFO Write Ready Read Ready Write Link Ready TX Clock Tx Clock

6. Shift Register Logic Port Transmitter “The Factory” Controller Dout Sout SpaceWire Character TX Clock DS Encoder TX DATA Control Signa ls Logic

7. Layer 2 (Character Level) Network Port Receiver D1117 SpaceWire Port Architecture Port Controller Din Sin Dout Sout Sys Clock Reset RX DATA / Control TX DATA / Control Link Start State Machine Transmitter FIFO RX CLOCK FIFO Write Ready Read Ready Write Link Ready Tx Clock

8. Port Receiver Shift Register MEM Error Reporting RX_DATA to FIFO RX Clock Recovery Din Sin Rx Clock Din Logic

9. Layer 2 (Character Level) Network Port Receiver D1117 SpaceWire Port Architecture Port Controller Din Sin Dout Sout Sys Clock Reset RX DATA / Control TX DATA / Control Link Start State Machine Transmitter FIFO RX CLOCK FIFO Write Ready Read Ready Write Link Ready Tx Clock

10. Internal Signals Transmitter Receiver P o r t C o n t r o l l e r ( S t a t e M a c h i n e ) RESET Send NULLs Send FCTs Send N-Chars Send Time-Codes GotFCT Got Time-Code GotN-Char GotNULL CreditError RX_Err RESET

11. Port Main Control – Overview Error Wait Reset Tx Enable Rx Error Wait Reset Tx Enable Rx Error Reset Reset Tx Reset Rx Error Reset Reset Tx Reset Rx Ready Reset Tx Enable Rx Ready Reset Tx Enable Rx Started Send Null Enable Rx Started Send Null Enable Rx Connecting Send Fct/Null Enable Rx Connecting Send Fct/Null Enable Rx Run Send All Enable Rx Run Send All Enable Rx After 6.4 ɥ s After 12.8 ɥ s [ Link Start ] Got Null Got Fct Rx Err OR Credit Error [Link Disabled] After 12.8 ɥ s Rx Err OR Got Fct Got NChar Rx Err OR Got Fct Got NChar Rx Err ORGot Fct Got NChar Rx Err OR After 12.8 ɥ s Got NChar ?

12. Port Main Control - Problem Error Wait Reset Tx Enable Rx Error Wait Reset Tx Enable Rx Error Reset Reset Tx Reset Rx Error Reset Reset Tx Reset Rx Ready Reset Tx Enable Rx Ready Reset Tx Enable Rx Started Send Null Enable Rx Started Send Null Enable Rx Connecting Send Fct/Null Enable Rx Connecting Send Fct/Null Enable Rx Run Send All Enable Rx Run Send All Enable Rx After 6.4 ɥ s After 12.8 ɥ s [ Link Start ] Got Null Got FCT Rx Err OR Credit Error [Link Disabled] A f t e r 1 2. 8 ɥ s Rx Err OR Got FCT Got NChar Rx Err OR Got FCT Got NChar Rx Err ORGot FCT Got NChar Rx Err OR After 12.8 ɥ s Got NChar

13. Port Main Control - Resolution Error Wait Reset Tx Enable Rx Error Wait Reset Tx Enable Rx Error Reset Reset Tx Reset Rx Error Reset Reset Tx Reset Rx Ready Reset Tx Enable Rx Ready Reset Tx Enable Rx Started Send Null Enable Rx Started Send Null Enable Rx Connecting Send Fct/Null Enable Rx Connecting Send Fct/Null Enable Rx Run Send All Enable Rx Run Send All Enable Rx After 6.4 ɥ s After 12.8 ɥ s [ Link Start ] Got Null Got FCT Rx Err OR Credit Error [Link Disabled] After 12.8 ɥ s Rx Err OR Got FCT Got NChar Rx Err OR Got FCT Got NChar Rx Err ORGot FCT Got NChar Rx Err OR After 12.8 ɥ s Got NChar

14. Receiver Port Controller Din Sin Dout Sout Sys Clock Reset RX DATA / Control TX DATA / Control Link Start State Machine FIFO RX CLOCK FIFO Write Ready Read Ready Write Tx Clock Link Ready Layer 2 (Character Level) Network Port Transmitter D1117 SpaceWire Port LVDS Interface LVDS Drivers Din+ Din- Sin+ Sin- Dout+ Sout+ Sout- Dout-

15. SpaceWire Interface SpaceWire connectors are driven by Low Voltage Differential Signaling (LVDS) system (2.5 Volts). Signal conversion to LVDS is required. SpaceWire connectors are driven by Low Voltage Differential Signaling (LVDS) system (2.5 Volts). Signal conversion to LVDS is required. Inner shield Din+ Din- Sin- Sout+ Dout+ Sin+ Sout- Dout- SpaceWire PinOut

16. Testing The Core Programming GR-RASTA Board (based on VirtexII) with the SpaceWire Port’s Core.Programming GR-RASTA Board (based on VirtexII) with the SpaceWire Port’s Core. Connecting the RASTA-Board SPW interface to Gaisler’s GRESB SpaceWire Bridge. Verifying correctness of our core by sending megabytes of files between our port and the GRESB bridge and vice versa. iMPACT monitoring

17. Project Milestones Focus on the Router Examination of several switching architectures. Designing the network configuration and layout. Implementation of the router core and supporting logics. Validating correctness of the router. Examination of several switching architectures. Designing the network configuration and layout. Implementation of the router core and supporting logics. Validating correctness of the router.