ELEC 5270/6270 Spring 2011 Low-Power Design of Electronic Circuits Adiabatic Logic Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Spr11/course.html Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 8

Examples of Power Saving and Energy Recovery Power saving by power transmission at high voltage: 1000W transmitted at 100V, current I = 10A If resistance of transmission circuit is 1Ω, then power loss = I2R = 100W Transmit at 1000V, current I = 1A, transmission loss = 1W Energy recovery from automobile braking: Normal brake converts mechanical energy into heat Instead, the energy can be stored in a flywheel, or Converted to electricity to charge a battery Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 8

Reexamine CMOS Gate V2/ Rp V Most energy dissipated here i2Rp i = Ve–t/RpC/Rp v(t) Power v(t) V×i = V2e–2t/RpC/ Rp C V v(t) 3RpC Time, t Energy dissipation per transition = Area/2 = C V 2/ 2 Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 8

Charging with Constant Current V(t) i2Rp i = constant it/C V v(t) = it/C C2V2Rp/T2 Output voltage, v(t) Power C T=CV/i Time, t Time (T) to charge capacitor to voltage V v(T) = V = iT/C, or T = CV/i Current, i = CV/T Power = i2Rp = C2V2Rp/T2 Energy dissipation = Power × T = (RpC/T) CV2 Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 8

Or, Charge in Steps 0→V/2→V i2Rp i = Ve–t/RpC/2Rp V2e–2t/RpC/4Rp v(t) V2/4Rp C V v(t) Power V/2 3RpC 6RpC Energy = Area = CV2/8 Time, t Total energy = CV2/8 + CV2/8 = CV2/4 Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 8

Energy Dissipation of a Step Voltage step = V/N T E = ∫ V2e–2t/RpC/(N2Rp) dt = [CV2/(2N2)] (1 – e–2T/RpC) ≈ CV2/(2N2) for large T ≥ 3RpC Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 8

Charge in N Steps Supply voltage 0 → V/N → 2V/N → 3V/N → . . . NV/N Current, i(t) = Ve–t/RpC/NRp Power, i2(t)Rp = V2e–2t/RpC/N2Rp Energy = N CV2/2N2 = CV2/2N → 0 for N → ∞ Delay = N × 3RpC → ∞ for N → ∞ Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 8

Reexamine Charging of a Capacitor v(t) i(t) C V Charge on capacitor, q(t) = C v(t) Current, i(t) = dq(t)/dt = C dv(t)/dt Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 8

∫ ───── = ∫ ──── i(t) = C dv(t)/dt = [V – v(t)] /R dv(t) V – v(t) ─── = ───── dt RC dv(t) dt ∫ ───── = ∫ ──── V – v(t) RC – t ln [V – v(t)] = ── + A RC Initial condition, t = 0, v(t) = 0 → A = ln V – t v(t) = V [1 – exp(───)] RC Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 8

– t v(t) = V [1 – exp( ── )] RC dv(t) V – t i(t) = C ─── = ── exp( ── ) dt R RC Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 8

Total Energy Per Charging Transition from Power Supply ∞ ∞ V 2 – t Etrans = ∫ V i(t) dt = ∫ ── exp( ── ) dt 0 0 R RC = CV2 Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 8

Energy Dissipated per Transition in Resistance ∞ V 2 ∞ –2t R ∫ i 2(t) dt = R ── ∫ exp( ── ) dt 0 R2 0 RC 1 = ─ CV 2 2 Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 8

Energy Stored in Charged Capacitor ∞ ∞ – t V – t ∫ v(t) i(t) dt = ∫ V [1– exp( ── )] ─ exp( ── ) dt 0 0 RC R RC 1 = ─ CV 2 2 Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 8

Slow Charging of a Capacitor v(t) i(t) C V(t) Charge on capacitor, q(t) = C v(t) Current, i(t) = dq(t)/dt = C dv(t)/dt Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 8

∫ ────── = ∫ ──── i(t) = C dv(t)/dt = [V(t) – v(t)] /R dv(t) V(t) – v(t) ─── = ───── dt RC dv(t) dt ∫ ────── = ∫ ──── V(t) – v(t) RC Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 8

Effects of Slow Charging Voltage across R Voltage V(t) v(t) t Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 8

Constant Current Is Optimum I(t) R t = [0,T] V C Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 8

Average and Instantaneous Current Let T be the time to charge C to voltage V T Average current : (1/T) ∫ I(t) dt = I0 Instantaneous current: I(t) = I0 + i(t) Where ∫ i(t) dt = 0 Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 8

Energy Dissipation E = R ∫ I2(t) dt = R ∫ [I0 + i(t)]2 dt 0 0 T 0 0 T = R ∫ [I02 + 2I0i(t) + i2(t)] dt T T = RI02T + 2RI0 ∫ i(t) dt + R ∫ i2(t) dt 0 0 = RI02T + 0 + R ∫ i2(t) dt ≥ RI02T = RI02T, minimum value, when i(t) = 0, i.e., I(t) = I0 Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 8

Minimum Energy For a constant current I0, Charging time, T = CV/I0 Emin = RCVI0 Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 8

References C. L. Seitz, A. H. Frey, S. Mattisson, S. D. Rabin, D. A. Speck and J. L. A. van de Snepscheut, “Hot-Clock nMOS,” Proc. Chapel Hill Conf. VLSI, 1985, pp. 1-17. W. C. Athas, L. J. Swensson, J. D. Koller, N. Tzartzanis and E. Y.-C. Chou, “Low-Power Digital Systems Based on Adiabatic-Switching Principles,” IEEE Trans. VLSI Systems, vol. 2, no. 4, pp. 398-407, Dec. 1994. Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 8

A Conventional Dynamic CMOS Inverter CK vin v(t) P E P E P E CK v(t) vin C Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 8

Adiabatic Dynamic CMOS Inverter P E P E P E P E V CK vin v(t) v(t) vin C Vf + V-Vf CK A. G. Dickinson and J. S. Denker, “Adiabatic Dynamic Logic,” IEEE J. Solid-State Circuits, vol. 30, pp. 311-315, March 1995. Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 8

Cascaded Adiabatic Inverters vin CK1 CK2 CK1’ CK2’ input CK1 CK2 CK1’ CK2’ precharge evaluate hold Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 8

Complex ADL Gate AB + C A C Vf < Vth B CK A. G. Dickinson and J. S. Denker, “Adiabatic Dynamic Logic,” IEEE J. Solid-State Circuits, vol. 30, pp. 311-315, March 1995. Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 8

Clocks EVAL. HOLD EVAL. HOLD VDD  VDD  Copyright Agrawal, 2007 VDD  Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 8

Quasi-Adiabatic Logic Design Possible Cases: The circuit output node X is LOW and the pMOS tree is turned ON: X follows  as it swings to HIGH (EVALUATE phase) The circuit node X is LOW and the nMOS tree is ON. X remains LOW and no transition occurs (HOLD phase) The circuit node X is HIGH and the pMOS tree is ON. X remains HIGH and no transition occurs (HOLD phase) The circuit node X is HIGH and the nMOS tree is ON. X follows  down to LOW. Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 8

A Case Study K. Parameswaran, “Low Power Design of a 32-bit Quasi-Adiabatic ARM Based Microprocessor,” Master’s Thesis, Dept. of ECE, Rutgers University, New Brunswick, NJ, 2004. Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 8

Quasi-Adiabatic 32-bit ARM Based Microprocessor Design Specifications Operating voltage: 2.5 V Operating temperature: 25oC Operating frequency: 10 MHz to 100 MHz Leakage current: 0.5 fAmps Load capacitance: 6X10-18 F (15% activity) Transistor Count: Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 8

Technology Distribution Microprocessor has a mix of static CMOS and Quasi-adiabatic components Quasi-Adiabatic Static CMOS ALU Adder-subtractor unit Barrel shifter unit Booth-multiplier Control Units ARM controller unit Bus control unit Pipeline Units ID unit IF unit WB unit MEM unit Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 8

Power Consumption (mW) Power Consumption (mW) Power Analysis Datapath Component Power Consumption (mW) Frequency 25 MHz Frequency 100 MHz Quasi-adiabatic Static CMOS Power Saved 32-bit Adder Subtracter 1.01 1.55 44% 1.29 1.62 20% 32-bit Barrel Shifter 0.9 1.681 46% 1.368 1.8 24% 32-bit Booth Multiplier 3.4 5.8 40% 5.15 6.2 17% Power Consumption (mW) Frequency 25 MHz Quasi-adiabatic Static CMOS Power Saved 60 mW 85 mW 40% Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 8

Power Analysis (Cont’d.) Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 8

Area Analysis Datapath Component Area (mm2) Quasi-adiabatic Static CMOS Area Increase 32-bit Adder Subtracter 0.05 0.03 66% 32-bit Barrel Shifter 0.25 0.11 120% 32-bit Booth Multiplier 1.2 0.5 140% Chip Area (mm2) Quasi-adiabatic Static CMOS Area Increase 1.55 1.01 44% Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 8

Summary In principle, two types of adiabatic logic designs have been proposed: Fully-adiabatic Adiabatic charging Charge recovery: charge from a discharging capacitor is used to charge the capacitance from the next stage. W. C. Athas, L. J. Swensson, J. D. Koller, N. Tzartzanis and E. Y.-C. Chou, “Low-Power Digital Systems Based on Adiabatic-Switching Principles,” IEEE Trans. VLSI Systems, vol. 2, no. 4, pp. 398-407, Dec. 1994. Quasi-adiabatic Adiabatic charging and discharging Y. Ye and K. Roy, “QSERL: Quasi-Static Energy Recovery Logic,” IEEE J. Solid-State Circuits, vol. 36, pp. 239-248, Feb. 2001. Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 8