Computer Architecture and Organization: L10: I/O Instruction and interrupt By: A. H. Abdul Hafez Abdul.hafez@hku.edu.tr, ah.abdulhafez@gmail.com, hafez@research.iiit.ac.in CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU November 18, 2018

Outlines Input / Output configuration and operations I/O instructions Program interrupt Flowchart for interrupt cycle Basic computer design End CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU November 18, 2018

Decode operation code in IR (12-14) AR  IR(0-11), I  IR(15) Start SC  0 T0 AR  PC T1 IR  M[AR], PC  PC+1 T2 Decode operation code in IR (12-14) AR  IR(0-11), I  IR(15) (Register or I/O) =1 D7 =0 (Memory-reference) ( I/O ) =1 I =0 (register) (indirect ) =1 I =0 (direct ) D7 I T3 T3 D7 I T3 D7 I T3 T3 T3 D7 I T3 T3 Execute input-output Instruction SC  0 Execute Register-refernce Instruction SC  0 AR  M[AR] Nothing Execute Memory-reference Instruction SC  0 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU November 18, 2018 Flowchart for instruction cycle (initial configuration)

Input-Output Configuration The terminal devices send and receive serial information. The INPR and OUTR communicate serially with terminals and in parallel with the AC. FGI and FGO are two single bit flip-flops needed to synchronize the timing rate difference between the terminals and the computer.

Input operation Initially, FGI is cleared to 0. When a key is struck in the keyboard, an 8-bit code is shifted into INPR and the input flag FGI IS SET TO 1. As long as the flag FGI=1, the content of INPR cannot be changed with a new code. The computer checks the FGI flag, if it is 1, the information in INPR is transferred into AC in parallel and the FGI is cleared to 0. Once the flag is cleared, new information code can be shifted into INPR by striking another key. FGO Receiver interface Printer OUTR AC Transmitter interface Keyboard INPR 00110110 01110111 FGI 1

Output operation Initially, FGO is set to 1. The computer checks the flag bit, if it is 1, the information from AC is transferred in parallel into OUTR and FGO is cleared to 0. The output device accepts the coded information, prints the corresponding character, and when the operation is completed, it sets FGO to 1. As long as the flag FGO is cleared, the computer does not load a new character code into OUTR. FGO 1 Receiver interface Printer OUTR AC 00110110 Transmitter interface Keyboard INPR FGI November 18, 2018 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU

Input-Output Instructions Input-output instructions are needed for transferring information to and from AC register, for checking the input and output flags and for controlling the interrupt facility. Input-output instructions have op-code 1111 and are recognized when D7=1 and I=1. The execution of all input-output instructions is done during timing signal T3. D7 I T3 =p (common for all input-output instructions) IR( I ) = Bi [bit in IR (6-11) that specifies the instructions] p: SC ← 0 Clear SC INP pB11: AC(0-7) ←INPR, FGI ← 0 Input character OUT pB10: OUTR ←AC (0-7), FGO ← 0 Output character SKI pB9: if (FGI=1) then (PC ←PC + 1) Skip on input flag SKO pB8: if (FGO=1) then (PC ←PC + 1) Skip on output flag ION pB7: IEN ← 1 Interrupt enable ON IOF pB6: IEN ←0 Interrupt enable OFF

Program Interrupt The process of communication with I/O devices through the continuous checking of the FGI and FGO flags is called programmed control transfer. The computer through the this process is wasting time while checking the flag instead of doing some other useful processing task. Assume that the computer goes through the instruction cycle in 1 µs and the I/O device can transfer the data at a rate of 10 character per second. This is equivalent to one character every 100000 µs. The computer executes two instructions to check the flag bit and to decide not to transfer information. Two instructions executed through 2 µs == i.e the computer checks the flag 50000 times between each transfer!!! It’s a wasting of time. Instead, is to let the external device inform the computer when it is ready for the transfer. This is done through the using of interrupt facility. CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU November 18, 2018

A number of Flip-Flops are needed to perform the interrupt operation: R: Interrupt flip-flop. IEN: Interrupt enable flip-flop FGI: input flag flip-flop FGO: output flag flip-flop IEN can be set and cleared by the user with the two instructions ION and IOF. When IEN is set to 1 by the instruction ION the interrupt for the computer is allowed, otherwise (i.e. when IEN=0) the interrupt is not allowed. The interrupt flip-flop R is set to 1 when IEN=1 AND either FGI or FGO is equal to 1. CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU November 18, 2018

When R=0, the computer goes through the instruction cycle When R=0, the computer goes through the instruction cycle. And during the execution phase of the instruction cycle, the computer control circuit checks the IEN flip-flop. If IEN=0, it is an indication that the user does not want to use interrupt. If IEN=1, control circuit checks the flags FGI and FGO. If both flags are 0 (FGI=FGO=0), it indicates that neither input nor output registers are ready for transfer operation. If either flag is set to 1 while IEN=1, flip-flop R is set to 1. At the end of the execute phase, the control circuit checks R, if it is 1, the computer goes through interrupt cycle instead of instruction cycle. During interrupt cycle, the microoperations are: RT0: AR ← 0, TR ← PC RT1: M[AR] ← TR, PC ← 0 RT2: PC ← PC + 1, IEN ← 0, R ← 0, SC ← 0 November 18, 2018 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU

T0’T1’T2’ IEN (FGI + FGO): R ← 1 The interrupt flip-flop R is set to 1 when IEN=1 AND either FGI or FGO is equal to 1. This can be happened with any timing signals except T0,T1 and T2. Therefore the condition for setting R is: T0’T1’T2’ IEN (FGI + FGO): R ← 1 Therefore, the control functions for the fetch and decode phases of the instruction cycles should be changed to be: R’T0: AR ← PC R’T1: IR ← M[AR], PC ← PC + 1 R’T2: I ← IR (15), D7…..D0 ← IR (12-14), AR ← IR (0-11) The input-output service routine is designed to start from a certain location (EX: (800)16 ). And a jump for this location is done by a direct BUN instruction ( 0 BUN 800 ) located at memory location ( 1 )16. The last instruction in the input-output service routine should be indirect BUN instruction (1 BUN 0) to read the return address from the memory location ( 0 )16. See flowchart in the next slide for details. CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU November 18, 2018

Flowchart for interrupt cycle Fetch and decode instruction Store return address in memory location 0 M[0] ← PC Execute instruction Branch to location 1 PC ← 1 IEN FGI FGO IEN ← 0 R ← 0 R ← 1 = 1 = 0 Interrupt cycle Instruction cycle Interrupt Flip Flop CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU November 18, 2018

Demonstration of interrupt cycle Memory Memory 0 BUN 800 I/O Program 1 BUN 0 256 PC= 1 PC= 1 0 BUN 800 Main Program 255 PC=256 Main Program 255 PC=256 800 800 I/O program 1 BUN 0 Indirect branch (a) Before interrupt (b) After interrupt cycle. November 18, 2018 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU

Decode operation code in IR (12-14) Start SC  0, IEN ← 0, R ← 0 (instruction cycle) = 0 1 = (interrupt cycle) R R’T0 RT0 AR  PC AR  0, TR ← PC R’T1 RT1 M[AR] TR, PC  0 IR  M[AR], PC  PC+1 R’T2 RT2 PC ← PC + 1, IEN ← 0 R  0, SC  0 Decode operation code in IR (12-14) AR  IR(0-11), I  IR(15) (Register or I/O) =1 D7 =0 (Memory-reference) ( I/O ) =1 I =0 (register) (indirect ) =1 I =0 (direct ) D7 I T3 D7 I T3 T3 D7 I T3 T3 T3 D7 I T3 T3 Execute input-output Instruction SC  0 Execute Register-refernce Instruction SC  0 AR  M[AR] Nothing Execute Memory-refernce Instruction SC  0 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU November 18, 2018

CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU November 18, 2018

COMPLETE COMPUTER DESCRIPTION Flowchart of Operations start SC <- 0, IEN <- 0, R <- 0 =0(Instruction =1(Interrupt Cycle) Cycle) R R’T0 RT0 AR <- PC AR <- 0, TR <- PC R’T1 RT1 IR <- M[AR], PC <- PC + 1 M[AR] <- TR, PC <- 0 R’T2 RT2 AR <- IR(0~11), I <- IR(15) D0...D7 <- Decode IR(12 ~ 14) PC <- PC + 1, IEN <- 0 R <- 0, SC <- 0 =1(Register or I/O) =0(Memory Ref) D7 =1 (I/O) =0 (Register) =1(Indir) =0(Dir) I I D7IT3 D7I’T3 D7’IT3 D7’I’T3 Execute I/O Instruction Execute RR Instruction AR <- M[AR] Idle Execute MR Instruction D7’T4

T0’T1’T2’ IEN (FGI + FGO): R ← 1 Table (5-6) Control Functions and Microoperations for the basic computer (Mano computer) Register Reference D7 I’ T3 = r IR( I ) = Bi [bit in IR (0-11) that specifies the operation] r: SC ← 0 CLA rB11: AC ← 0 CLE rB10: E ← 0 CMA rB9: AC ← AC CME rB8: E ← E CIR rB7: AC ← shr AC, AC(15) ← E, E← AC (0) CIL rB6: AC ← shl AC, AC(0) ← E, E← AC (15) INC rB5: AC ← AC+1 SPA rB4: If (AC (15)=0) then (PC← PC+1) SNA rB3: If (AC (15)=1) then (PC← PC+1) SZA rB2: If (AC =0) then (PC← PC+1) SZE rB1: If (E=0) then (PC← PC+1) HLT rB0: S← 0 (S is a start-stop flip-flop) Fetch R’T0: R’T1: AR ← PC IR ← M[AR], PC ← PC + 1 Decode R’T2: D0….D7 ← IR (12-14), I ← IR (15), AR ← IR (0-11) Indirect D7’IT3: AR ← M[AR] Interrupt T0’T1’T2’ IEN (FGI + FGO): R ← 1 RT0: AR ← 0, TR ← PC RT1: M[AR] ← TR, PC ← 0 RT2: PC ← PC + 1, IEN ← 0, R ← 0, SC ← 0 Memory Reference AND D0T4: D0T5: DR ← M[AR] AC← AC ^ DR, SC← 0 ADD D1T4: D1T5: AC← AC ^ DR, E ← Cout, SC← 0 LDA D2T4: D2T5: DR← M[AR] AC← DR, SC← 0 STA D3T4: M[AR]← AC, SC← 0 BUN D4T4: PC← AR, SC← 0 BSA D5T4: D5T5: M[AR] ← PC, AR← AR+1 ISZ D6T4: D6T5: D6T6: DR ← DR + 1 M[AR] ← DR, if DR=0 then PC ← PC + 1 Input-output D7 I T3 =p (common for all input-output instructions) IR( I ) = Bi [bit in IR (6-11) that specifies the instructions] p: SC ← 0 INP pB11: AC(0-7) ←INPR, FGI ← 0 OUT pB10: OUTR ←AC (0-7), FGO ← 0 SKI pB9: if (FGI=1) then (PC ←PC + 1) SKO pB8: if (FGO=1) then (PC ←PC + 1) ION pB7: IEN ← 1 IOF pB6: IEN ←0

Design of Basic Computer The proposed basic computer consists of the following hardware components: 1- A memory unit with 4096 words of 16 bits each. 2- Nine registers : AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC. 3- Seven Flip Flops: I, S, E, R, IEN, FGI, and FGO. 4- Two decoders: 3-to-8 op-code decoder and 4-to-16 timing decoder. 5- 16-bit common bus. 6- Control logic gates. 7- Adder and logic circuit connected to the input of the accumulator. November 18, 2018 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU

S E R IEN FGI FGO DR instruction register (IR) AC 15 14 13 12 11-0 3x8 decoder Control logic gates 7 6 5 4 3 2 1 0 D0 ... D7 I T15 ... T0 . . . 15 14 .... 2 1 0 4x6 decoder (INR) 4-bit Sequence Counter (SC) (CLR) Clock

The end of the Lecture Thanks for your time Questions are welcome CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU November 18, 2018