1. Basic architecture

2. Computer Architecture definition:
Computer Architecture refers to how a computer system is designed and what technologies it is compatible with.

3. Von Neuman Archeticture
This is a general depiction of a von Neumann system:
These computers employ a fetch-decode-execute cycle to run programs as follows . . .
Hold data and instructions

4. INSTRUCTION
Program:
A set of instructions that specify the operations, operands, and the sequence by which processing has to occur.
Instruction Code:
A group of bits that tell the computer to perform a specific operation
(a sequence of micro-operation)
The instructions of a program, along with any needed data are stored in
memory. يتم تخزين تعليمات البرنامج، جنبا إلى جنب مع أي البيانات أخرى لازمة في الذاكرة.
The CPU reads the next instruction from memory. وحدة المعالجة المركزية يقرأ التعليمة التالية من الذاكرة.
It is placed in an Instruction Register (IR). يتم وضعها في مسجل التعليمة.
Control circuitry in control unit then translates the instruction into the
sequence of microoperations necessary to implement it. ثم تترجم دائرة التحكم في وحدة التحكم التعليمات إلى سلسلة التعليمات الدقيقة اللازمة لتنفيذ ذلك

5. INSTRUCTION FORMAT
A computer instruction is often divided into two parts:
An opcode (Operation Code) that specifies the operation for that instruction
An address that specifies the registers and/or locations in memory to use for that operation
In the Basic Computer, since the memory contains 4096 (=212) words, we needs 12 bit to specify which memory address this instruction will use

6. INSTRUCTION FORMAT
In the Basic Computer, bit 15 of the instruction specifies the addressing mode (0: direct addressing, 1: indirect addressing)
Since the memory words, and hence the instructions, are 16 bits long, that leaves 3 bits for the instruction’s opcode
Opcode
Address
Instruction Format 15 14 12 I 11
Addressing
mode

7. The address field of an instruction can represent either
ADDRESSING MODES
The address field of an instruction can represent either
Direct address: the address in memory of the data to use (the address of the operand), or
Indirect address: the address in memory of the address in memory of the data to use
ADD
457 22
Operand 1
300 35
1350 + AC
Direct addressing
Indirect addressing

8. BASIC COMPUTER REGISTERS
Registers in the Basic Computer 11 PC
Memory 11
4096 x 16 AR 15 IR
CPU 15 15 TR DR 7 7 15
OUTR
INPR AC
List of BC Registers
DR Data Register Holds memory operand
AR Address Register Holds address for memory
AC Accumulator Processor register
IR Instruction Register Holds instruction code
PC Program Counter Holds address of instruction
TR Temporary Register Holds temporary data
INPR Input Register Holds input character
OUTR Output Register Holds output character

9. COMMON BUS SYSTEM
The registers in the Basic Computer are connected using a bus
This gives a savings in circuitry over complete connections between registers

10. BASIC COMPUTER(BC) INSTRUCTIONS
Basic Computer Instruction code format
Memory-Reference Instructions (OP-code = 000 ~ 110)
12 11 I
Opcode
Address
Register-Reference Instructions (OP-code = 111, I = 0) 15
12 11
Register operation
Input-Output Instructions (OP-code =111, I = 1) 15
12 11
I/O operation

11. BASIC COMPUTER INSTRUCTIONS
Hex Code
Symbol I = I = Description
AND xxx 8xxx AND memory word to AC
ADD xxx 9xxx Add memory word to AC
LDA xxx Axxx Load AC from memory
STA xxx Bxxx Store content of AC into memory
BUN xxx Cxxx Branch unconditionally
BSA xxx Dxxx Branch and save return address
ISZ xxx Exxx Increment and skip if zero
CLA Clear AC
CLE Clear E
CMA Complement AC
CME Complement E
CIR Circulate right AC and E
CIL Circulate left AC and E
INC Increment AC
SPA Skip next instr. if AC is positive
SNA Skip next instr. if AC is negative
SZA Skip next instr. if AC is zero
SZE Skip next instr. if E is zero
HLT Halt computer
INP F Input character to AC
OUT F Output character from AC
SKI F Skip on input flag
SKO F Skip on output flag
ION F Interrupt on
IOF F Interrupt off

12. INSTRUCTION SET COMPLETENESS
A computer should have a set of instructions so that the user can
construct machine language programs to evaluate any function that is
known to be computable.
Instruction Types:
Functional Instructions
- Arithmetic, logic, and shift instructions
- ADD, CMA, INC, CIR, CIL, AND, CLA
Transfer Instructions
- Data transfers between the main memory
and the processor registers
- LDA, STA
Control Instructions
- Program sequencing and control
- BUN, BSA, ISZ
Input/Output Instructions
- Input and output
- INP, OUT

13. Instruction execution cycle
program counter
instruction queue
Fetch
Decode
Fetch operands
Execute
Store output

14. Computer System performance evaluation:
Computer performance is characterized by the amount of useful work accomplished by a computer system or computer network compared to the time and resources used.
To evaluate CS performance:
Short response time for a given work(time the system take to react to a given input)
High throughput(rate of processing work)

15. Computer System performance evaluation
Low utilization of computing resource)
high availability of the computing system or application
Fast (or highly compact) data compression and decompression

16. INSTRUCTION CYCLE
In Basic Computer, a machine instruction is executed in the following cycle:
Fetch an instruction from memory: جلب التعليمة من الذاكرة
Decode the instruction: فك شفرة التعليمة
Read the effective address from memory if the instruction has an indirect address :قراءة العنوان الفعال من الذاكرة إذا كانت التعليمة لديها عنوان غير مباشر
Execute the instruction: تنفيذ التعليمة
After an instruction is executed, the cycle starts again at step 1, for the next instruction
Note: Every different processor has its own (different) instruction cycle

17. INSTRUCTION CYCLE
Initially, the Program Counter (PC) is loaded with the address of the first instruction in the program
The sequence counter SC is cleared to 0, providing a decoded timing signal T0
After each clock pulse, SC is incremented by one, so that the timing signals go through a sequence T0, T1, T2, and so on

18. T0: AR←PC (this is essential!!)
INSTRUCTION CYCLE
T0: AR←PC (this is essential!!)
The address of the instruction is moved to AR.
T1: IR←M[AR], PC←PC+1
The instruction is fetched from the memory to IR ,
and the PC is incremented.
T2: D0,…, D7←Decode IR(12-14), AR←IR(0-11), I←IR(15)

19. INSTRUCTION CYCLE • Fetch and Decode T1 S2 T0 S1 S0 7 Address Read 1
T0: AR PC (S0S1S2=010, T0=1)
T1: IR  M [AR], PC  PC (S0S1S2=111, T1=1)
T2: D0, , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15) T1 S2 T0 S1
Bus S0
Memory
unit 7
Address
Read AR 1 LD PC 2
INR IR 5 LD
Clock
Common bus

20. Enhancing Computer System performance evaluation
Enhancing Computer System performance with pipelining technique
Sequential laundry

21. Enhancing Computer System performance evaluation
Enhancing Computer System performance evaluation with pipelining technique
pipeline laundry

22. Instruction Pipelining
Technique used to enhance CPU performance by increase it’s speed in performing tasks related to instructions

23. Instruction Pipelining

24. Advanced architecture
Pipelining

25. What is Pipelining
A technique used in advanced microprocessors where the microprocessor begins executing a second instruction before the first has been completed.
A Pipeline is a series of stages, where some work is done at each stage. The work is not finished until it has passed through all stages.
With pipelining, the computer architecture allows the next instructions to be fetched while the processor is performing arithmetic operations, holding them in a buffer close to the processor until each instruction operation can performed.

26. How Pipelines Works
The pipeline is divided into segments and each segment can execute it operation concurrently with the other segments. Once a segment completes an operations, it passes the result to the next segment in the pipeline and fetches the next operations from the preceding segment.

27. How Pipelines Works
Pipelining makes it possible for processor to execute instructions in parallel
Instruction execution divided into discrete stages
Example of a non-pipelined processor. For example, Many wasted cycles.

28. Pipelined execution
More efficient use of cycles, greater throughput of instructions: (80486 started to use pipelining)
For k stages and n instructions, the number of required cycles is:
k + (n – 1)
compared to k*n

29. Instructions Fetch
The instruction Fetch (IF) stage is responsible for obtaining the requested instruction from memory. The instruction and the program counter (which is incremented to the next instruction) are stored in the IF/ID pipeline register as temporary storage so that may be used in the next stage at the start of the next clock cycle.

30. Instruction Decode
The Instruction Decode (ID) stage is responsible for decoding the instruction and sending out the various control lines to the other parts of the processor. The instruction is sent to the control unit where it is decoded and the registers are fetched from the register file.

31. Execution
The Execution (EX) stage is where any calculations are performed. The main component in this stage is the ALU. The ALU is made up of arithmetic, logic and capabilities.

32. Memory and IO
The Memory and IO (MEM) stage is responsible for storing and loading values to and from memory. It also responsible for input or output from the processor. If the current instruction is not of Memory or IO type than the result from the ALU is passed through to the write back stage.

33. Write Back
The Write Back (WB) stage is responsible for writing the result of a calculation, memory access or input into the register file.

34. Operation Timings Instruction Fetch 2ns Instruction Decode 1ns
Estimated timings for each of the stages:
Instruction Fetch
2ns
Instruction Decode
1ns
Execution
Memory and IO
Write Back

35. Advantages/Disadvantages
More efficient use of processor
Quicker time of execution of large number of
instructions
Disadvantages:
Pipelining involves adding hardware to the chip
Inability to continuously run the pipeline
at full speed because of pipeline hazards
which disrupt the smooth execution of the
pipeline.

36. Pipeline Hazards
Data Hazards – an instruction uses the result of the previous instruction. A hazard occurs exactly when an instruction tries to read a register in its ID stage that an earlier instruction intends to write in its WB stage.
Control Hazards – the location of an instruction depends on previous instruction
Structural Hazards – two instructions need to access the same resource

37. Data Hazards

38. Stalling
Stalling involves halting the flow of instructions until the required result is ready to be used. However stalling wastes processor time by doing nothing while waiting for the result.

40. Type of Pipelining Software Pipelining
1) Can Handle Complex Instructions
2) Allows programs to be reused
Hardware Pipelining
1) Help designer manage complexity – a
complex task can be divided into smaller,
more manageable pieces.
2) Hardware pipelining offers higher
performance

41. Type of Hardware Pipelines
Instruction Pipeline - An instruction pipeline is very similar to a manufacturing assembly line.
1st stage receives some parts, performs its assembly task, and passes the results to the second stage;
2nd stage takes the partially assembled product from the first stage, performs its task, and passes its work to the third stage;
3rd stage does its work, passing the results to the last stage, which completes the task and outputs its results.
Data Pipeline – data pipeline is designed to pass data from stage to stage.

42. Instruction Pipelines Conflict
It divided into two categories.
Data Conflicts
Branch Conflicts
When the current instruction changes a register that the next one needed, data conflicts happens.
When the current instruction make a jump, branch conflicts happens.

43. References