1. Bus Architecture Memory unit AR PC DR E ALU AC INPR 16-bit Bus IR TR
Access
Select
Memory unit
4096x16
111 S1
address S0 AR
001 PC
010 DR
16-bit Bus
011 E
ALU AC
100
INPR IR
101 TR
110
OUTR
clock
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2. Instruction Format I opcode address I = 0 means direct memory address15 14 12 11 I
opcode
address
I = 0 means direct memory address
I = 1 means indirect memory address
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3. The Control Unit Control Unit Instruction Register (IR) 15 14 - 12
11 - 0
Other Inputs
3x8
Decoder 12
Control
Unit
D7 – D0 n I
T15 – T0
4x16
Decoder
Increment
Sequence
Counter
Clear
Master Clock
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4. Decoding the Instruction
We’ve seen how to fetch and decode instructions in RTL notation
We now need to look at how to execute each instruction T0 T1 T2
= 1, register or I/O
= 0, memory reference
= 1, I/O
= 0, register
= 1, indirect
= 0, direct T3 T3 T3 T3
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5. Register Instructions
These are all pretty simple
CLA D7I’T3B11: AC ← 0
CLE D7I’T3B10: E ← 0
CMA D7I’T3B9: AC ← AC’
CME D7I’T3B8: E ← E’
CIR D7I’T3B7: AC ← shr(AC),
AC(15) ← E, E ← AC(0)
CIL D7I’T3B6: AC ← shl(AC),
AC(0) ← E, E ← AC(15)
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6. Register Instructions
INC D7I’T3B5: AC ← AC + 1
SPA D7I’T3B4: if (AC(15) = 0)
then (PC ← PC + 1)
SNA D7I’T3B3: if (AC(15) = 1)
SZA D7I’T3B2: if (AC = 0) then (PC ← PC + 1)
SZE D7I’T3B1: if (E = 0) then (PC ← PC + 1)
HLT D7I’T3B0: S ← 0
S is a flip-flop that starts/stops the master clock
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7. Register Instructions
Perhaps the most interesting thing about these instructions is the condition on which each is selected
D7I’T3Bi
The D7I’terms specify the type of operation (register)
Execution starts at time T3 since no additional operands need to be fetched from memory
The Bi term is the interesting one
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8. Register Instructions
Note how the opcodes were assigned hex (binary) bit patterns
Notice any patterns?
Very common practice in both hardware design and programming
opcodes in hex
7800
7400
7200
7100
7080
7040
7020
7010
7008
7004
7002
7001
opcodes in binary
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9. Memory Instructions
The condition on which each is selected comes from the decoding of the operand and starts at time T4
DiT4
The Di term specifies the particular operation
Execution starts at time T4 assuring the operand has been fetched from the effective address
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10. Memory Instructions These are a bit more complex AND operation
D0: AC ← AC ^ M[AR]
This is fine except for the fact that the operation must take place in the ALU and M[AR] cannot be routed there directly
Therefore, we must rework this functional RTL statement to reflect the actual hardware architecture
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11. Logical AND We must first get M[AR] into the DR register
Then we can perform the AND operation
D0T4: DR ← M[AR]
D0T5: AC ← AC ^ DR, SC ← 0
Requires two timing phases, T4 and T5
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12. Arithmetic ADD Similar in nature to the AND operation D1T4: DR ← M[AR]
D1T5: AC ← AC + DR, E ← Cout, SC ← 0
The result remains in the AC register
If we want to place it in memory we must perform a store (STA) instruction
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13. Load Accumulator Similar in nature to the AND operation
D2T4: DR ← M[AR]
D2T5: AC ← DR, SC ← 0
Recall that the AC is only accessible through the ALU
This is why one of the ALU functions was a transfer (without any arithmetic operation)
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14. Store Accumulator Similar in nature to the AND operation
D3T4: M[AR] ← AC, SC ← 0
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15. Branch Unconditionally
A branch is merely a modification of the program counter (PC) register
D4T4: PC ← AR, SC ← 0
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16. Branch and Save Return Address
BSA is the assembly language version of a subroutine call
It must store the address of the next instruction (which is in the PC since we incremented it after the fetch cycle) somewhere
It uses the effective address of the operand for this purpose
It then performs a branch to the subroutine address
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17. Branch and Save Return Address
D5T4: M[AR] ← PC, AR ← AR + 1
D5T5: PC ← AR, SC ← 0
This means that the subroutine actually starts one memory location after that specified in the operand
Consider an example…
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18. Branch and Save Return Address
After time T5 (when the instruction is complete)
the PC is here
After time T3 the PC is here
BSA
0x50
0x20
0x21 1
BUN
SUBROUTINE CODE
0x51
BSA
0x50
0x20
0x21 1
BUN
SUBROUTINE CODE
0x51
BSA instruction inserts this at time T4
Programmer inserts this command
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19. Increment and Skip if Zero
This is used for creating for loops
Typically, you will store a negative loop count prior to using an ISZ command
It is also used in coordination with a BUN instruction
D6T4: DR ← M[AR]
D6T5: DR ← DR + 1
D6T6: M[AR] ← DR,
if (DR = 0) then (PC ← PC + 1),
SC ← 0
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20. Increment and Skip if Zero
STA
0xAA
0x20
0x21
ISZ
BUN
0xFFFC
0x50
0x51
Calculate loop count into AC
Store loop count
Start of loop
End of loop
-810
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21. Input/Output Instructions
Three new flip-flops are introduced into the architecture to support input/output commands
FGI – 1 when information from the input device is available, 0 otherwise
FGO – 1 when the output device is ready to receive information, 0 otherwise
IEN – interrupt enable
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22. Input/Output Instructions
D7IT3B11: AC(0-7) ← INPR, FGI ← 0, SC ← 0
OUT
D7IT3B10: OUTR ← AC(0-7), FGO ← 0, SC ← 0
SKI (used in a manner similar to the ISZ)
D7IT3B9: if (FGI = 1) then PC ← PC + 1, SC ← 0
SKO (used in a manner similar to the ISZ)
D7IT3B8: if (FGO = 1) then PC ← PC + 1, SC ← 0
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23. Input/Output Instructions
A problem arises when using the SKI and SKO instructions
Their purpose is to set up loop structures (similar to what we saw with the ISZ instruction) waiting for an input/output device to become available
This could cause large amounts of valuable time to be wasted
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24. Now for some more 8050 Assembly Language Programming
Subroutines
ACALL sub …
exit: jmp exit ; don’t let the main program run
; into the subroutine
sub:
ret
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25. What Does ACALL Do? Refer to page 17 of the programmer’s guide
Operation
(PC) ← (PC) + 2
(SP) ← (SP) + 1
(SP) ← (PC7-0)
(SP) ← (PC15-8)
(PC10-0) ← page address
a10 a9 a8 1 1 a7 a6 a5 a4 a3 a2 a1 a0
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26. ACALL Note that there is no parameter passage mechanism
How can I tell that?
Therefore, parameters and return values must be passed in memory or registers
You need to be careful about this
Is the memory used outside the subroutine?
Do the subroutines have to be reentrant?
etc.
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27. Programming Assignment
Previously you wrote code to determine if a number was prime
Place that code into a subroutine
Create a 2nd subroutine that is given a number in R0 and returns the next larger prime number in R1
This subroutine should call the subroutine for determining if a number is prime
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