An Overview of Silicon-on-Sapphire CMOS Technologies Garrett Zook EECS 713

What is Silicon-on-Sapphire? Invented in 1963 at NAA (now Boeing) First form of silicon-on-insulator (SOI) semiconductor technology Sapphire replaces standard silicon substrate material Original applications were one-off specialized rad-hard circuits Previously cost prohibitive, difficult to manufacture, economic barrier http://www.pitek.us/StackedDie.html

What makes SOS special? Nearly perfect insulator substrate Eliminates many parasitic capacitances Conducts heat well Robust to ionizing radiation True off state Benefits from all standard CMOS processing Can be manufactured in existing facilities Single crystal silicon Linear operation over large bandwidths Low power consumption Transparent substrate, easily integrates with optical devices

Popular CMOS technologies Silicon-on-sapphire CMOS BiCMOS Bulk silicon CMOS Faster than bulk CMOS Cheaper than BiCMOS Easy integration into large designs Much better adjacent device isolation Expensive to manufacture Complex, 12-step growth process Difficult integration with other technologies Widely used, cheap to manufacture Less power efficient Prone to latch-up

Extreme linearity Simple ESD protection SPEED Reduced bulk parasitics Significantly reduced CV2f power consumption CMOS requires bias current for proper operation 𝑔 𝑚 ∝ 1 𝑔𝑎𝑡𝑒 𝑙𝑒𝑛𝑔𝑡ℎ -> scale for better gm SOS CMOS simplified small-signal model compared to bulk CMOS

Fabrication process Uses Solid Phase Epitaxial Regrowth (SPER) Single crystal silicon Uses Solid Phase Epitaxial Regrowth (SPER) Silicon grown on sapphire substrate Anneal -> amorphize -> anneal Complicated processing to produce high yield MOSFET growth [6]

Substrate properties Single crystal Al2O3 Excellent insulator Sapphire [3] Silicon [7] Gallium Arsenide [7] Parameters Units AL2O3  Si GaAs Density g/cm3 3.97 2.3283 5.316 Thermal Conductivity W/m-K 42 83.5 46 Thermal Expansion ppm/°C 7.7 3 6 Specific Heat J/g-K 0.75 0.707 0.327 Electrical Resistivity Ω-cm 1014 230k 108 Rel. Dielectric Const.   11.5 12 12.9 Single crystal Al2O3 Excellent insulator Good thermal conductor

Radiation can wreak havoc on digital circuits Two main errors caused by ionizing radiation: Single event Total ionizing dose Implant/displace charges in transistors Can induce off-state currents Shift threshold voltages Total device failure

SOS CMOS is robust to ionizing radiation Immune (almost entirely) to single event effects Dopant profile is injected into channel to move the Fermi energy level Eliminates off-state current in P-channel devices SOS is naturally rad-hard Latch-up cannot occur due to complete isolation between NMOS and PMOS transistors http://www.intelligent-aerospace.com/articles/2013/03/Peregrine-Semi.html

Current technologies using SOS Farthest man-made object from Earth, Voyager 1 Commercially available RF switches, mixers, PLLs, digital attenuators, and more Handheld wireless devices are main source of SOS technology Spaceborne proprietary electronics

Peregrine UltraCMOS RF Switch [4] Functional operating range: 9 kHz – 60 GHz! Maximum of 2.7 dB insertion loss at 60 GHz Port isolation of >36 dB Operational temperatures: -55 °C to +125 °C Flip-chip die Immune to latch-up (most often caused by ionizing radiation) However, CMOS cannot handle high RF input power, <35 dBm

Resources [1] G. Imthurn, “ The History of Silicon-on-Sapphire,” white paper for Peregrine Semiconductor Corporation, 2007. [2] Cable, James S, et al. Radiation-Hardened Silicon-on-Insulator CMOS Device, and Method of Making the Same . 11 Mar. 2003. [3] Kyocera, “Single Crystal Sapphire,” 2017 Catalog. [4] Peregrine Semiconductor, “UltraCMOS SPDT RF Switch, 9 kHz – 60 GHz,” PE426525 datasheet, Dec. 2016 [5] G. A. Garcia, R. E. Reedy and M. L. Burgener, "High-quality CMOS in thin (100 nm) silicon on sapphire," in IEEE Electron Device Letters, vol. 9, no. 1, pp. 32-34, Jan. 1988. [6] Mark L. Burgener, Ronald E. Reedy, Minimum Charge FET Fabricated on an Ultrathin Silicon on Sapphire Wafer. 16 May 1995 [7] Allen, Christopher. “Higher Speed Digital Logic." EECS 713. University of Kansas. 28 Nov. 2017.

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